DE69031525D1 - Konfigurierbare Logikanordnung und zugehöriges Verfahren - Google Patents

Konfigurierbare Logikanordnung und zugehöriges Verfahren

Info

Publication number
DE69031525D1
DE69031525D1 DE69031525T DE69031525T DE69031525D1 DE 69031525 D1 DE69031525 D1 DE 69031525D1 DE 69031525 T DE69031525 T DE 69031525T DE 69031525 T DE69031525 T DE 69031525T DE 69031525 D1 DE69031525 D1 DE 69031525D1
Authority
DE
Germany
Prior art keywords
configurable logic
logic arrangement
associated procedure
procedure
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69031525T
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English (en)
Other versions
DE69031525T2 (de
Inventor
Ross H Freeman
Hung-Cheng Hsieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE69031525D1 publication Critical patent/DE69031525D1/de
Publication of DE69031525T2 publication Critical patent/DE69031525T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
DE69031525T 1989-07-28 1990-07-26 Konfigurierbare Logikanordnung und zugehöriges Verfahren Expired - Lifetime DE69031525T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/387,566 US5343406A (en) 1989-07-28 1989-07-28 Distributed memory architecture for a configurable logic array and method for using distributed memory

Publications (2)

Publication Number Publication Date
DE69031525D1 true DE69031525D1 (de) 1997-11-06
DE69031525T2 DE69031525T2 (de) 1998-01-29

Family

ID=23530436

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69031525T Expired - Lifetime DE69031525T2 (de) 1989-07-28 1990-07-26 Konfigurierbare Logikanordnung und zugehöriges Verfahren
DE199090308210T Pending DE410759T1 (de) 1989-07-28 1990-07-26 Konfigurierbare logikanordnung und zugehoeriges verfahren.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE199090308210T Pending DE410759T1 (de) 1989-07-28 1990-07-26 Konfigurierbare logikanordnung und zugehoeriges verfahren.

Country Status (5)

Country Link
US (3) US5343406A (de)
EP (1) EP0410759B1 (de)
JP (1) JP2703397B2 (de)
CA (1) CA2022056C (de)
DE (2) DE69031525T2 (de)

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JPH03132212A (ja) 1991-06-05
US5432719A (en) 1995-07-11
CA2022056A1 (en) 1991-01-29
JP2703397B2 (ja) 1998-01-26
EP0410759A2 (de) 1991-01-30
EP0410759A3 (en) 1992-05-27
US5488316A (en) 1996-01-30
US5343406A (en) 1994-08-30

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