DE69033398D1 - Rechnerarchitektur mit Mehrfachbefehlsausgabe - Google Patents

Rechnerarchitektur mit Mehrfachbefehlsausgabe

Info

Publication number
DE69033398D1
DE69033398D1 DE69033398T DE69033398T DE69033398D1 DE 69033398 D1 DE69033398 D1 DE 69033398D1 DE 69033398 T DE69033398 T DE 69033398T DE 69033398 T DE69033398 T DE 69033398T DE 69033398 D1 DE69033398 D1 DE 69033398D1
Authority
DE
Germany
Prior art keywords
command output
computer architecture
multiple command
architecture
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69033398T
Other languages
English (en)
Other versions
DE69033398T2 (de
Inventor
Robert W Horst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Application granted granted Critical
Publication of DE69033398D1 publication Critical patent/DE69033398D1/de
Publication of DE69033398T2 publication Critical patent/DE69033398T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134Register stacks; shift registers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22Microcontrol or microprogram arrangements
    • G06F9/26Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/261Microinstruction address formation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • G06F9/3844Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
DE69033398T 1989-05-24 1990-05-21 Rechnerarchitektur mit Mehrfachbefehlsausgabe Expired - Lifetime DE69033398T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US35617089A 1989-05-24 1989-05-24

Publications (2)

Publication Number Publication Date
DE69033398D1 true DE69033398D1 (de) 2000-01-27
DE69033398T2 DE69033398T2 (de) 2000-05-18

Family

ID=23400422

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033398T Expired - Lifetime DE69033398T2 (de) 1989-05-24 1990-05-21 Rechnerarchitektur mit Mehrfachbefehlsausgabe

Country Status (5)

Country Link
US (8) US5390355A (de)
EP (2) EP0902362A3 (de)
JP (1) JP2810211B2 (de)
CA (1) CA2016068C (de)
DE (1) DE69033398T2 (de)

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US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5826055A (en) * 1991-07-08 1998-10-20 Seiko Epson Corporation System and method for retiring instructions in a superscalar microprocessor
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
JP3730252B2 (ja) * 1992-03-31 2005-12-21 トランスメタ コーポレイション レジスタ名称変更方法及び名称変更システム
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EP0663083B1 (de) 1992-09-29 2000-12-20 Seiko Epson Corporation System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor
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US5490265A (en) * 1993-04-14 1996-02-06 Intel Corporation Late cancel method and apparatus for a high performance microprocessor system
US6138230A (en) * 1993-10-18 2000-10-24 Via-Cyrix, Inc. Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline
US5630149A (en) * 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
DE69408769T2 (de) * 1993-10-18 1998-07-09 Cyrix Corp Fliessbandsteuerung und Registerübersetzung in Mikroprozessor
US6073231A (en) * 1993-10-18 2000-06-06 Via-Cyrix, Inc. Pipelined processor with microcontrol of register translation hardware
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US5592488A (en) * 1995-06-07 1997-01-07 Micron Technology, Inc. Method and apparatus for pipelined multiplexing employing analog delays for a multiport interface
US5848288A (en) * 1995-09-20 1998-12-08 Intel Corporation Method and apparatus for accommodating different issue width implementations of VLIW architectures
JP2636821B2 (ja) * 1996-03-08 1997-07-30 株式会社日立製作所 並列処理装置
US5867681A (en) * 1996-05-23 1999-02-02 Lsi Logic Corporation Microprocessor having register dependent immediate decompression
US5794010A (en) * 1996-06-10 1998-08-11 Lsi Logic Corporation Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
US6065105A (en) * 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
US5838939A (en) * 1997-05-09 1998-11-17 Sun Microsystems, Inc. Multi-issue/plural counterflow pipeline processor
US6108768A (en) * 1998-04-22 2000-08-22 Sun Microsystems, Inc. Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system
US6742110B2 (en) * 1998-10-06 2004-05-25 Texas Instruments Incorporated Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution
US6192466B1 (en) * 1999-01-21 2001-02-20 International Business Machines Corporation Pipeline control for high-frequency pipelined designs
EP1050808B1 (de) * 1999-05-03 2008-04-30 STMicroelectronics S.A. Befehlausgabe in einem Rechner
EP1050809A1 (de) * 1999-05-03 2000-11-08 STMicroelectronics SA Befehlsabhängigkeit in einem Rechner
US6609191B1 (en) * 2000-03-07 2003-08-19 Ip-First, Llc Method and apparatus for speculative microinstruction pairing
US7149878B1 (en) * 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7711926B2 (en) * 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US6826681B2 (en) * 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
GB2424727B (en) * 2005-03-30 2007-08-01 Transitive Ltd Preparing instruction groups for a processor having a multiple issue ports

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Also Published As

Publication number Publication date
AU5515390A (en) 1990-11-29
AU630697B2 (en) 1992-11-05
US5390355A (en) 1995-02-14
CA2016068C (en) 2000-04-04
US5574941A (en) 1996-11-12
EP0902362A3 (de) 2001-10-04
US5918032A (en) 1999-06-29
JPH03116233A (ja) 1991-05-17
US5628024A (en) 1997-05-06
DE69033398T2 (de) 2000-05-18
CA2016068A1 (en) 1990-11-24
JP2810211B2 (ja) 1998-10-15
US5752064A (en) 1998-05-12
US6009506A (en) 1999-12-28
US6092177A (en) 2000-07-18
EP0399762B1 (de) 1999-12-22
US6266765B1 (en) 2001-07-24
EP0399762A2 (de) 1990-11-28
EP0399762A3 (de) 1992-01-22
EP0902362A2 (de) 1999-03-17

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