DE69033443D1 - Mechanismus zur Verzweigungsrücksetzung in einem Prozessor mit gepaarten Befehlen - Google Patents

Mechanismus zur Verzweigungsrücksetzung in einem Prozessor mit gepaarten Befehlen

Info

Publication number
DE69033443D1
DE69033443D1 DE69033443T DE69033443T DE69033443D1 DE 69033443 D1 DE69033443 D1 DE 69033443D1 DE 69033443 T DE69033443 T DE 69033443T DE 69033443 T DE69033443 T DE 69033443T DE 69033443 D1 DE69033443 D1 DE 69033443D1
Authority
DE
Germany
Prior art keywords
reset mechanism
instruction processor
paired instruction
branch reset
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69033443T
Other languages
English (en)
Other versions
DE69033443T2 (de
Inventor
Robert L Jardine
Shannon J Lynch
Philip R Manela
Robert W Horst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Publication of DE69033443D1 publication Critical patent/DE69033443D1/de
Application granted granted Critical
Publication of DE69033443T2 publication Critical patent/DE69033443T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
DE69033443T 1989-05-24 1990-05-21 Mechanismus zur Verzweigungsrücksetzung in einem Prozessor mit gepaarten Befehlen Expired - Lifetime DE69033443T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/356,316 US5072364A (en) 1989-05-24 1989-05-24 Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel

Publications (2)

Publication Number Publication Date
DE69033443D1 true DE69033443D1 (de) 2000-03-09
DE69033443T2 DE69033443T2 (de) 2000-06-29

Family

ID=23400969

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033443T Expired - Lifetime DE69033443T2 (de) 1989-05-24 1990-05-21 Mechanismus zur Verzweigungsrücksetzung in einem Prozessor mit gepaarten Befehlen

Country Status (6)

Country Link
US (1) US5072364A (de)
EP (2) EP0939364A3 (de)
JP (1) JP2846406B2 (de)
AU (1) AU631874B2 (de)
CA (1) CA2016254A1 (de)
DE (1) DE69033443T2 (de)

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CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
JPH0795271B2 (ja) * 1989-06-20 1995-10-11 富士通株式会社 分岐命令実行装置
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5185871A (en) * 1989-12-26 1993-02-09 International Business Machines Corporation Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
JP2834292B2 (ja) * 1990-08-15 1998-12-09 株式会社日立製作所 データ・プロセッサ
US5442772A (en) * 1991-03-29 1995-08-15 International Business Machines Corporation Common breakpoint in virtual time logic simulation for parallel processors
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5826055A (en) * 1991-07-08 1998-10-20 Seiko Epson Corporation System and method for retiring instructions in a superscalar microprocessor
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
DE4237417C2 (de) * 1992-03-25 1997-01-30 Hewlett Packard Co Datenverarbeitungssystem
WO1993020505A2 (en) 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
DE69308548T2 (de) 1992-05-01 1997-06-12 Seiko Epson Corp Vorrichtung und verfahren zum befehlsabschluss in einem superskalaren prozessor.
JP2922723B2 (ja) * 1992-06-29 1999-07-26 キヤノン株式会社 情報処理装置
CA2105806C (en) * 1992-09-18 2001-11-20 Paul V. Jeffs Apparatus for implementing interrupts in pipelined processors
US5617549A (en) * 1992-10-06 1997-04-01 Hewlett-Packard Co System and method for selecting and buffering even and odd instructions for simultaneous execution in a computer
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
EP0682789B1 (de) * 1992-12-31 1998-09-09 Seiko Epson Corporation System und verfahren zur änderung der namen von registern
US6032244A (en) * 1993-01-04 2000-02-29 Cornell Research Foundation, Inc. Multiple issue static speculative instruction scheduling with path tag and precise interrupt handling
US5748976A (en) * 1993-10-18 1998-05-05 Amdahl Corporation Mechanism for maintaining data coherency in a branch history instruction cache
WO1995016952A1 (en) * 1993-12-15 1995-06-22 Silicon Graphics Inc. Superscalar microprocessor instruction pipeline including instruction dispatch and release control
DK0661625T3 (da) * 1994-01-03 2000-04-03 Intel Corp Fremgangsmåde og apparatur til implementering af et firetrins system til bestemmelse af programforgreninger (Four Stage Bra
US5809271A (en) * 1994-03-01 1998-09-15 Intel Corporation Method and apparatus for changing flow of control in a processor
US5644779A (en) * 1994-04-15 1997-07-01 International Business Machines Corporation Processing system and method of operation for concurrent processing of branch instructions with cancelling of processing of a branch instruction
US5623694A (en) * 1994-10-03 1997-04-22 International Business Machines Corporation Aborting an I/O operation started before all system data is received by the I/O controller after detecting a remote retry operation
US5625808A (en) * 1995-03-31 1997-04-29 International Business Machines Corporation Read only store as part of cache store for storing frequently used millicode instructions
US5634103A (en) * 1995-11-09 1997-05-27 International Business Machines Corporation Method and system for minimizing branch misprediction penalties within a processor
JPH09319569A (ja) * 1996-05-31 1997-12-12 Mitsubishi Electric Corp マイクロコンピュータ
KR100445054B1 (ko) * 1996-06-29 2004-11-02 주식회사 하이닉스반도체 마이크로프로세서의브랜치처리를위한방법
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US5974538A (en) * 1997-02-21 1999-10-26 Wilmot, Ii; Richard Byron Method and apparatus for annotating operands in a computer system with source instruction identifiers
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US6055630A (en) * 1998-04-20 2000-04-25 Intel Corporation System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units
SE9901146D0 (sv) * 1998-11-16 1999-03-29 Ericsson Telefon Ab L M A processing system and method
SE9901145D0 (sv) 1998-11-16 1999-03-29 Ericsson Telefon Ab L M A processing system and method
EP1131703A1 (de) * 1998-11-16 2001-09-12 Telefonaktiebolaget Lm Ericsson Simultanes verarbeitungssystem für veranstaltungsbasierte systeme
SE9803901D0 (sv) * 1998-11-16 1998-11-16 Ericsson Telefon Ab L M a device for a service network
GB2355084B (en) * 1999-07-21 2004-04-28 Element 14 Ltd Setting condition values in a computer
GB2403833B (en) * 2000-02-16 2005-02-23 Hewlett Packard Co Method and apparatus for resteering failing speculation check instructions field
US6636960B1 (en) * 2000-02-16 2003-10-21 Hewlett-Packard Development Company, L.P. Method and apparatus for resteering failing speculation check instructions
DE10101949C1 (de) * 2001-01-17 2002-08-08 Infineon Technologies Ag Datenverarbeitungsverfahren
US7747843B2 (en) * 2004-06-02 2010-06-29 Broadcom Corporation Microprocessor with integrated high speed memory
US7216218B2 (en) * 2004-06-02 2007-05-08 Broadcom Corporation Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations
US11144364B2 (en) 2019-01-25 2021-10-12 International Business Machines Corporation Supporting speculative microprocessor instruction execution

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US4398243A (en) * 1980-04-25 1983-08-09 Data General Corporation Data processing system having a unique instruction processor system
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
US4685058A (en) * 1983-08-29 1987-08-04 Amdahl Corporation Two-stage pipelined execution unit and control stores
JPH0769818B2 (ja) * 1984-10-31 1995-07-31 株式会社日立製作所 デ−タ処理装置
US4777587A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
EP0239081B1 (de) * 1986-03-26 1995-09-06 Hitachi, Ltd. Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen
DE68926701T2 (de) * 1988-08-09 1997-02-20 Matsushita Electric Ind Co Ltd Datenverarbeitungsgerät zur parallelen Dekodierung und parallelen Ausführung von Befehlen mit variabler Wortlänge

Also Published As

Publication number Publication date
EP0399760B1 (de) 2000-02-02
CA2016254A1 (en) 1990-11-23
EP0939364A2 (de) 1999-09-01
JP2846406B2 (ja) 1999-01-13
EP0399760A2 (de) 1990-11-28
AU631874B2 (en) 1992-12-10
JPH03116235A (ja) 1991-05-17
EP0399760A3 (de) 1993-05-19
DE69033443T2 (de) 2000-06-29
EP0939364A3 (de) 2001-06-27
US5072364A (en) 1991-12-10
AU5504790A (en) 1990-11-29

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