DE69033912D1 - Anordnung zur Reparatur eines fehlerhaften Bits in einer Halbleiterspeichervorrichtung und Verfahren zur Reparatur - Google Patents

Anordnung zur Reparatur eines fehlerhaften Bits in einer Halbleiterspeichervorrichtung und Verfahren zur Reparatur

Info

Publication number
DE69033912D1
DE69033912D1 DE69033912T DE69033912T DE69033912D1 DE 69033912 D1 DE69033912 D1 DE 69033912D1 DE 69033912 T DE69033912 T DE 69033912T DE 69033912 T DE69033912 T DE 69033912T DE 69033912 D1 DE69033912 D1 DE 69033912D1
Authority
DE
Germany
Prior art keywords
circuit
row
decoder
repair
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69033912T
Other languages
English (en)
Other versions
DE69033912T2 (de
Inventor
Shuji Murakami
Tomohisa Wada
Kenji Anami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69033912D1 publication Critical patent/DE69033912D1/de
Publication of DE69033912T2 publication Critical patent/DE69033912T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
DE69033912T 1989-06-05 1990-02-26 Anordnung zur Reparatur eines fehlerhaften Bits in einer Halbleiterspeichervorrichtung und Verfahren zur Reparatur Expired - Fee Related DE69033912T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1142450A JP2837433B2 (ja) 1989-06-05 1989-06-05 半導体記憶装置における不良ビット救済回路

Publications (2)

Publication Number Publication Date
DE69033912D1 true DE69033912D1 (de) 2002-03-14
DE69033912T2 DE69033912T2 (de) 2002-08-22

Family

ID=15315593

Family Applications (3)

Application Number Title Priority Date Filing Date
DE69033912T Expired - Fee Related DE69033912T2 (de) 1989-06-05 1990-02-26 Anordnung zur Reparatur eines fehlerhaften Bits in einer Halbleiterspeichervorrichtung und Verfahren zur Reparatur
DE69033977T Expired - Fee Related DE69033977T2 (de) 1989-06-05 1990-02-26 Anordnung zur Reparatur eines fehlerhaften Bits in einer Halbleiterspeichervorrichtung und Verfahren zur Reparatur
DE69033976T Expired - Fee Related DE69033976T2 (de) 1989-06-05 1990-02-26 Anordnung zur Reparatur eines fehlerhaften Bits in einer Halbleiterspeichervorrichtung und Verfahren zur Reparatur

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE69033977T Expired - Fee Related DE69033977T2 (de) 1989-06-05 1990-02-26 Anordnung zur Reparatur eines fehlerhaften Bits in einer Halbleiterspeichervorrichtung und Verfahren zur Reparatur
DE69033976T Expired - Fee Related DE69033976T2 (de) 1989-06-05 1990-02-26 Anordnung zur Reparatur eines fehlerhaften Bits in einer Halbleiterspeichervorrichtung und Verfahren zur Reparatur

Country Status (4)

Country Link
US (2) US5134585A (de)
EP (5) EP0858033B1 (de)
JP (1) JP2837433B2 (de)
DE (3) DE69033912T2 (de)

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JP2870320B2 (ja) * 1992-09-29 1999-03-17 日本電気株式会社 半導体メモリ回路
JP2980472B2 (ja) * 1992-12-21 1999-11-22 株式会社東芝 半導体記憶装置
JPH0793172A (ja) * 1993-09-24 1995-04-07 Nec Corp 冗長ブロック切り替え回路
JP3249871B2 (ja) * 1993-12-22 2002-01-21 三菱電機株式会社 半導体記憶装置
JP3351595B2 (ja) * 1993-12-22 2002-11-25 株式会社日立製作所 半導体メモリ装置
JPH07182893A (ja) * 1993-12-24 1995-07-21 Mitsubishi Electric Corp 半導体記憶装置
US5440246A (en) * 1994-03-22 1995-08-08 Mosel Vitelic, Incorporated Programmable circuit with fusible latch
US5815512A (en) * 1994-05-26 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory testing device
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
JP3553138B2 (ja) * 1994-07-14 2004-08-11 株式会社ルネサステクノロジ 半導体記憶装置
US5457656A (en) * 1994-08-17 1995-10-10 United Microelectronics Corp. Zero static power memory device redundancy circuitry
JP3691113B2 (ja) * 1995-06-07 2005-08-31 株式会社ルネサステクノロジ メモリ回路、メモリ回路のデータ制御回路、およびメモリ回路のアドレス指定回路
WO1996041264A1 (en) * 1995-06-07 1996-12-19 International Business Machines Corporation Static wordline redundancy memory device
KR0172745B1 (ko) * 1995-12-29 1999-03-30 김주용 플래쉬 메모리 장치
JP3501893B2 (ja) * 1996-02-23 2004-03-02 株式会社 沖マイクロデザイン 半導体記憶装置
US5793942A (en) * 1996-03-26 1998-08-11 Lucent Technologies Inc. Memory chip architecture and packaging method for increased production yield
US6057221A (en) * 1997-04-03 2000-05-02 Massachusetts Institute Of Technology Laser-induced cutting of metal interconnect
US5889414A (en) * 1997-04-28 1999-03-30 Mosel Vitelic Corporation Programmable circuits
US5835431A (en) * 1997-09-05 1998-11-10 Integrated Device Technology, Inc. Method and apparatus for wafer test of redundant circuitry
KR100252053B1 (ko) 1997-12-04 2000-05-01 윤종용 칼럼 방향의 데이터 입출력선을 가지는 반도체메모리장치와불량셀 구제회로 및 방법
US6163492A (en) 1998-10-23 2000-12-19 Mosel Vitelic, Inc. Programmable latches that include non-volatile programmable elements
US6084803A (en) * 1998-10-23 2000-07-04 Mosel Vitelic, Inc. Initialization of non-volatile programmable latches in circuits in which an initialization operation is performed
US6408401B1 (en) * 1998-11-13 2002-06-18 Compaq Information Technologies Group, L.P. Embedded RAM with self-test and self-repair with spare rows and columns
DE10012104C2 (de) * 2000-03-13 2002-05-02 Infineon Technologies Ag Redundanz-Multiplexer für Halbleiterspeicheranordnung
US6262935B1 (en) * 2000-06-17 2001-07-17 United Memories, Inc. Shift redundancy scheme for wordlines in memory circuits
JP2002008389A (ja) 2000-06-20 2002-01-11 Mitsubishi Electric Corp 半導体記憶装置
US6373757B1 (en) 2000-07-17 2002-04-16 Integrated Device Technology, Inc. Integrated circuit memory devices having control circuits therein that provide column redundancy capability
US6496427B2 (en) * 2000-08-28 2002-12-17 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device
US6418068B1 (en) 2001-01-19 2002-07-09 Hewlett-Packard Co. Self-healing memory
US6643195B2 (en) 2002-01-11 2003-11-04 Hewlett-Packard Development Company, Lp. Self-healing MRAM
US7117400B2 (en) * 2002-11-13 2006-10-03 International Business Machines Corporation Memory device with data line steering and bitline redundancy
US8234543B2 (en) * 2009-03-06 2012-07-31 Via Technologies, Inc. Detection and correction of fuse re-growth in a microprocessor
US8281222B2 (en) * 2009-08-07 2012-10-02 Via Technologies, Inc. Detection and correction of fuse re-growth in a microprocessor
DE102009058540A1 (de) 2009-12-16 2011-05-26 Daimler Ag Außenrückspiegel für ein Kraftfahrzeug
KR20170016640A (ko) * 2015-08-04 2017-02-14 에스케이하이닉스 주식회사 반도체 장치 및 그 리페어 방법

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JPS56111194A (en) 1980-01-18 1981-09-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor memory
US4389715A (en) 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
EP0090331B1 (de) * 1982-03-25 1991-04-17 Kabushiki Kaisha Toshiba Halbleiterspeicheranordnung
JPS59144098A (ja) * 1983-02-08 1984-08-17 Fujitsu Ltd 半導体記憶装置
JPS6093700A (ja) * 1983-10-26 1985-05-25 Hitachi Ltd ライン切換回路およびそれを用いた半導体記憶装置
US4703436A (en) * 1984-02-01 1987-10-27 Inova Microelectronics Corporation Wafer level integration technique
GB2154032B (en) * 1984-02-08 1988-04-20 Inmos Ltd A repairable memory array
JPS6135636A (ja) 1984-07-27 1986-02-20 Sony Corp 光信号伝送装置
JPS6161300A (ja) * 1984-09-03 1986-03-29 Hitachi Ltd 欠陥救済回路
FR2576133B1 (fr) * 1985-01-15 1991-04-26 Eurotechnique Sa Memoire en circuit integre a haute fiabilite
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Also Published As

Publication number Publication date
EP0858032A2 (de) 1998-08-12
JP2837433B2 (ja) 1998-12-16
DE69033976T2 (de) 2002-10-02
DE69033912T2 (de) 2002-08-22
EP1197864A3 (de) 2004-09-22
JPH038200A (ja) 1991-01-16
EP0858033A2 (de) 1998-08-12
EP0401957A2 (de) 1990-12-12
EP0858032A3 (de) 1998-08-19
US5134585A (en) 1992-07-28
DE69033977T2 (de) 2002-11-28
EP0858032B1 (de) 2002-01-30
EP0401957A3 (de) 1992-05-27
EP0858033A3 (de) 1998-08-19
EP1197864A2 (de) 2002-04-17
EP0856793B1 (de) 2002-06-19
EP0856793A2 (de) 1998-08-05
DE69033977D1 (de) 2002-07-25
EP0856793A3 (de) 1998-08-19
US5379258A (en) 1995-01-03
DE69033976D1 (de) 2002-07-25
EP0858033B1 (de) 2002-06-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee