DE69106944D1 - Hochintegrierte EPROM-Zelle mit gestapeltem und geteiltem Gate mit vor Kurzschlüssen und Unterbrechungen geschützter Bitleitung. - Google Patents

Hochintegrierte EPROM-Zelle mit gestapeltem und geteiltem Gate mit vor Kurzschlüssen und Unterbrechungen geschützter Bitleitung.

Info

Publication number
DE69106944D1
DE69106944D1 DE69106944T DE69106944T DE69106944D1 DE 69106944 D1 DE69106944 D1 DE 69106944D1 DE 69106944 T DE69106944 T DE 69106944T DE 69106944 T DE69106944 T DE 69106944T DE 69106944 D1 DE69106944 D1 DE 69106944D1
Authority
DE
Germany
Prior art keywords
interruptions
stacked
bit line
short circuits
highly integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69106944T
Other languages
English (en)
Other versions
DE69106944T2 (de
Inventor
Albert M Bergemont
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69106944D1 publication Critical patent/DE69106944D1/de
Publication of DE69106944T2 publication Critical patent/DE69106944T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE69106944T 1990-06-28 1991-06-14 Hochintegrierte EPROM-Zelle mit gestapeltem und geteiltem Gate mit vor Kurzschlüssen und Unterbrechungen geschützter Bitleitung. Expired - Lifetime DE69106944T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/545,396 US5091327A (en) 1990-06-28 1990-06-28 Fabrication of a high density stacked gate eprom split cell with bit line reach-through and interruption immunity

Publications (2)

Publication Number Publication Date
DE69106944D1 true DE69106944D1 (de) 1995-03-09
DE69106944T2 DE69106944T2 (de) 1995-10-05

Family

ID=24176050

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69106944T Expired - Lifetime DE69106944T2 (de) 1990-06-28 1991-06-14 Hochintegrierte EPROM-Zelle mit gestapeltem und geteiltem Gate mit vor Kurzschlüssen und Unterbrechungen geschützter Bitleitung.

Country Status (5)

Country Link
US (1) US5091327A (de)
EP (1) EP0463510B1 (de)
JP (1) JPH07135266A (de)
KR (1) KR100231962B1 (de)
DE (1) DE69106944T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2685373B2 (ja) * 1991-06-28 1997-12-03 シャープ株式会社 不揮発性半導体記憶装置の製造方法
JP3043135B2 (ja) * 1991-09-26 2000-05-22 新日本製鐵株式会社 不揮発性半導体メモリの製造方法
US5654568A (en) * 1992-01-17 1997-08-05 Rohm Co., Ltd. Semiconductor device including nonvolatile memories
US6004829A (en) * 1997-09-12 1999-12-21 Taiwan Semiconductor Manufacturing Company Method of increasing end point detection capability of reactive ion etching by adding pad area
US6017791A (en) * 1997-11-10 2000-01-25 Taiwan Semiconductor Manufacturing Company Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer
JP2001168306A (ja) * 1999-12-09 2001-06-22 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US6300220B1 (en) * 2000-01-06 2001-10-09 National Semiconductor Corporation Process for fabricating isolation structure for IC featuring grown and buried field oxide
KR100442090B1 (ko) * 2002-03-28 2004-07-27 삼성전자주식회사 분할된 게이트 구조를 갖는 비휘발성 메모리 셀들 및 그제조방법
US6858494B2 (en) 2002-08-20 2005-02-22 Taiwan Semiconductor Manufacturing Company Structure and fabricating method with self-aligned bit line contact to word line in split gate flash
US7256112B2 (en) * 2005-01-20 2007-08-14 Chartered Semiconductor Manufacturing, Ltd Laser activation of implanted contact plug for memory bitline fabrication
CN107706228A (zh) * 2017-08-31 2018-02-16 上海华虹宏力半导体制造有限公司 沟槽栅超结器件及其制造方法
CN107591440A (zh) * 2017-08-31 2018-01-16 上海华虹宏力半导体制造有限公司 沟槽栅超结器件及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60234372A (ja) * 1984-05-07 1985-11-21 Toshiba Corp 半導体装置の製造方法
US4639893A (en) * 1984-05-15 1987-01-27 Wafer Scale Integration, Inc. Self-aligned split gate EPROM
US4795719A (en) * 1984-05-15 1989-01-03 Waferscale Integration, Inc. Self-aligned split gate eprom process
JPS61136274A (ja) * 1984-12-07 1986-06-24 Toshiba Corp 半導体装置
US4892840A (en) * 1986-03-27 1990-01-09 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
US4698900A (en) * 1986-03-27 1987-10-13 Texas Instruments Incorporated Method of making a non-volatile memory having dielectric filled trenches
FR2621737B1 (fr) * 1987-10-09 1991-04-05 Thomson Semiconducteurs Memoire en circuit integre

Also Published As

Publication number Publication date
KR100231962B1 (ko) 1999-12-01
US5091327A (en) 1992-02-25
EP0463510A2 (de) 1992-01-02
DE69106944T2 (de) 1995-10-05
JPH07135266A (ja) 1995-05-23
EP0463510A3 (en) 1993-03-31
KR920001734A (ko) 1992-01-30
EP0463510B1 (de) 1995-01-25

Similar Documents

Publication Publication Date Title
DE69107808T2 (de) Festkörper-Speichermodule und Speicheranordnungen mit solchen Modulen.
DE69327033T2 (de) Multiebenenkonferenz-Verwaltung und Benachrichtung
FR2671223B1 (fr) Memoire semiconductrice remanente pour ordinateur personnel.
FR2679729B1 (fr) Dissipateur thermique.
DE69326310T2 (de) Halbleiterspeichervorrichtung mit geteilter Wortleitungsstruktur
DE69332857D1 (de) Halbleitervorrichtung.
DE68917226D1 (de) Gegen die Polaritätsumkehr seiner Versorgungsbatterie geschützte elektronische Schaltung.
FI103924B1 (fi) Kannettavan tietokoneen lukitusväline
DE68921368D1 (de) Gate-Abschalthalbleitereinrichtung.
DE69106944T2 (de) Hochintegrierte EPROM-Zelle mit gestapeltem und geteiltem Gate mit vor Kurzschlüssen und Unterbrechungen geschützter Bitleitung.
DE69015228D1 (de) Halbleitervorrichtung mit Kaskaden-modulations-dotierten Potentialtopf-Heterostrukturen.
DE68921900T2 (de) Halbleiterspeicheranordnung mit serieller Zugriffsanordnung.
DE69423329T2 (de) Halbleiterspeicher mit sehr schnellem Leseverstärker
DE69317562D1 (de) Halbleiteranordnung mit doppelgate.
DE69111252D1 (de) Halbleiter-Speichereinrichtung mit Monitor-Funktion.
DE69321993D1 (de) Bitleitungsabtastung in Halbleiterspeicheranordnungen
DE68913868D1 (de) Supraleitender Transistor.
DE69327135T2 (de) Halbleiteranordnung mit mehreren Halbleiterchips
DE69202363D1 (de) Halbleiteranordnung.
DE59200257D1 (de) Schiebetor.
DE69201708D1 (de) Feldeffekttransistor.
DE69310559D1 (de) Schaltungs-Halbleiterbauteil mit Gate
IT1215769B (it) Dispositivo di sbarramento antifumo in ambienti chiusi.
DE68923343T2 (de) NAND Gateschaltungen.
NO910177L (no) Port.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition