DE69113571D1 - MIS-Transistor mit Heteroübergang. - Google Patents

MIS-Transistor mit Heteroübergang.

Info

Publication number
DE69113571D1
DE69113571D1 DE69113571T DE69113571T DE69113571D1 DE 69113571 D1 DE69113571 D1 DE 69113571D1 DE 69113571 T DE69113571 T DE 69113571T DE 69113571 T DE69113571 T DE 69113571T DE 69113571 D1 DE69113571 D1 DE 69113571D1
Authority
DE
Germany
Prior art keywords
heterojunction
mis transistor
mis
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69113571T
Other languages
English (en)
Other versions
DE69113571T2 (de
Inventor
Toru Koizumi
Hidemasa Mizutani
Masakazu Morishita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69113571D1 publication Critical patent/DE69113571D1/de
Publication of DE69113571T2 publication Critical patent/DE69113571T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
DE69113571T 1990-10-31 1991-10-30 MIS-Transistor mit Heteroübergang. Expired - Fee Related DE69113571T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP29212190 1990-10-31
JP29212090 1990-10-31
JP29211990 1990-10-31
JP2145191 1991-01-23

Publications (2)

Publication Number Publication Date
DE69113571D1 true DE69113571D1 (de) 1995-11-09
DE69113571T2 DE69113571T2 (de) 1996-03-28

Family

ID=27457583

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69113571T Expired - Fee Related DE69113571T2 (de) 1990-10-31 1991-10-30 MIS-Transistor mit Heteroübergang.

Country Status (5)

Country Link
US (1) US5475244A (de)
EP (1) EP0483824B1 (de)
JP (1) JP2947654B2 (de)
CA (1) CA2054498C (de)
DE (1) DE69113571T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5728592A (en) * 1992-10-09 1998-03-17 Fujitsu Ltd. Method for fabricating a thin film transistor matrix device
JP3437863B2 (ja) 1993-01-18 2003-08-18 株式会社半導体エネルギー研究所 Mis型半導体装置の作製方法
JPH06310719A (ja) * 1993-04-19 1994-11-04 Sharp Corp Ge−SiのSOI型MOSトランジスタ及びその製造方法
US5581092A (en) * 1993-09-07 1996-12-03 Semiconductor Energy Laboratory Co., Ltd. Gate insulated semiconductor device
TW297142B (de) 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
US6777763B1 (en) * 1993-10-01 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
JP3030368B2 (ja) * 1993-10-01 2000-04-10 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
KR0135804B1 (ko) * 1994-06-13 1998-04-24 김광호 실리콘 온 인슐레이터(soi) 트랜지스터
JP3361922B2 (ja) * 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3243146B2 (ja) 1994-12-08 2002-01-07 株式会社東芝 半導体装置
US5773328A (en) * 1995-02-28 1998-06-30 Sgs-Thomson Microelectronics, Inc. Method of making a fully-dielectric-isolated fet
US6870232B1 (en) * 1996-07-18 2005-03-22 International Business Machines Corporation Scalable MOS field effect transistor
JPH1140811A (ja) 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US6060749A (en) * 1998-04-23 2000-05-09 Texas Instruments - Acer Incorporated Ultra-short channel elevated S/D MOSFETS formed on an ultra-thin SOI substrate
US6124627A (en) * 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US7262105B2 (en) * 2003-11-21 2007-08-28 Freescale Semiconductor, Inc. Semiconductor device with silicided source/drains
FR2868207B1 (fr) * 2004-03-25 2006-09-08 Commissariat Energie Atomique Transistor a effet de champ a materiaux de source, de drain et de canal adaptes et circuit integre comportant un tel transistor
US7825400B2 (en) 2006-06-09 2010-11-02 Intel Corporation Strain-inducing semiconductor regions
JP2009054719A (ja) * 2007-08-24 2009-03-12 Tokyo Electron Ltd 半導体製造方法、半導体製造装置および表示装置
US7750368B2 (en) * 2008-06-13 2010-07-06 Macronix International Co., Ltd. Memory device
US9818744B2 (en) * 2014-09-04 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Leakage current suppression methods and related structures

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59231865A (ja) * 1983-06-14 1984-12-26 Seiko Epson Corp 半導体装置
JPS60224274A (ja) * 1984-04-20 1985-11-08 Nec Corp 絶縁基板mis型電界効果トランジスタの製造方法
US4673957A (en) * 1984-05-14 1987-06-16 Energy Conversion Devices, Inc. Integrated circuit compatible thin film field effect transistor and method of making same
US4727044A (en) * 1984-05-18 1988-02-23 Semiconductor Energy Laboratory Co., Ltd. Method of making a thin film transistor with laser recrystallized source and drain
JPS6156460A (ja) * 1984-08-28 1986-03-22 Nec Corp 半導体装置及びその製造方法
US4603471A (en) * 1984-09-06 1986-08-05 Fairchild Semiconductor Corporation Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
JPS62131573A (ja) * 1985-12-04 1987-06-13 Hitachi Ltd 半導体装置
JPS63252478A (ja) * 1987-04-09 1988-10-19 Seiko Instr & Electronics Ltd 絶縁ゲ−ト型半導体装置
GB2211022B (en) * 1987-10-09 1991-10-09 Marconi Electronic Devices A semiconductor device and a process for making the device
JP2841419B2 (ja) * 1988-02-19 1998-12-24 株式会社デンソー 多結晶ダイオードおよびその製造方法
US5142641A (en) * 1988-03-23 1992-08-25 Fujitsu Limited CMOS structure for eliminating latch-up of parasitic thyristor
JPH01248668A (ja) * 1988-03-30 1989-10-04 Seiko Epson Corp 薄膜トランジスタ
JPH01276765A (ja) * 1988-04-28 1989-11-07 Seiko Epson Corp 薄膜トランジスタ
JPH02188967A (ja) * 1989-01-18 1990-07-25 Nissan Motor Co Ltd 半導体装置
JP2698182B2 (ja) * 1989-07-31 1998-01-19 三洋電機株式会社 薄膜トランジスタ
JP2888878B2 (ja) * 1989-10-02 1999-05-10 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
EP0483824A1 (de) 1992-05-06
CA2054498C (en) 1997-05-20
JP2947654B2 (ja) 1999-09-13
DE69113571T2 (de) 1996-03-28
CA2054498A1 (en) 1992-05-01
US5475244A (en) 1995-12-12
JPH053322A (ja) 1993-01-08
EP0483824B1 (de) 1995-10-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee