DE69114333D1 - Rechner mit der Fähigkeit mehrere Befehle gleichzeitig auszuführen. - Google Patents

Rechner mit der Fähigkeit mehrere Befehle gleichzeitig auszuführen.

Info

Publication number
DE69114333D1
DE69114333D1 DE69114333T DE69114333T DE69114333D1 DE 69114333 D1 DE69114333 D1 DE 69114333D1 DE 69114333 T DE69114333 T DE 69114333T DE 69114333 T DE69114333 T DE 69114333T DE 69114333 D1 DE69114333 D1 DE 69114333D1
Authority
DE
Germany
Prior art keywords
ability
computer
same time
several commands
execute several
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69114333T
Other languages
English (en)
Other versions
DE69114333T2 (de
Inventor
Mitsuo Saito
Kenji Minagawa
Takeshi Aikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69114333D1 publication Critical patent/DE69114333D1/de
Publication of DE69114333T2 publication Critical patent/DE69114333T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69114333T 1990-03-30 1991-03-28 Rechner mit der Fähigkeit mehrere Befehle gleichzeitig auszuführen. Expired - Fee Related DE69114333T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2084607A JP2818249B2 (ja) 1990-03-30 1990-03-30 電子計算機

Publications (2)

Publication Number Publication Date
DE69114333D1 true DE69114333D1 (de) 1995-12-14
DE69114333T2 DE69114333T2 (de) 1996-05-15

Family

ID=13835379

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114333T Expired - Fee Related DE69114333T2 (de) 1990-03-30 1991-03-28 Rechner mit der Fähigkeit mehrere Befehle gleichzeitig auszuführen.

Country Status (4)

Country Link
US (1) US5377339A (de)
EP (1) EP0449661B1 (de)
JP (1) JP2818249B2 (de)
DE (1) DE69114333T2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69123629T2 (de) * 1990-05-04 1997-06-12 Ibm Maschinenarchitektur für skalaren Verbundbefehlssatz
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
GB9027853D0 (en) * 1990-12-21 1991-02-13 Inmos Ltd Multiple instruction issue
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
JP2779557B2 (ja) * 1991-07-09 1998-07-23 三菱電機株式会社 並列演算処理装置
EP0636256B1 (de) 1992-03-31 1997-06-04 Seiko Epson Corporation Befehlsablauffolgeplanung von einem risc-superskalarprozessor
DE69308548T2 (de) 1992-05-01 1997-06-12 Seiko Epson Corp Vorrichtung und verfahren zum befehlsabschluss in einem superskalaren prozessor.
DE69330889T2 (de) 1992-12-31 2002-03-28 Seiko Epson Corp System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
DE69430018T2 (de) * 1993-11-05 2002-11-21 Intergraph Corp Befehlscachespeicher mit assoziativem Kreuzschienenschalter
US6360313B1 (en) 1993-11-05 2002-03-19 Intergraph Corporation Instruction cache associative crossbar switch
EP0950946B1 (de) * 1993-11-05 2001-08-16 Intergraph Corporation Superskalare Rechnerarchitektur mit Softwarescheduling
WO1995016952A1 (en) * 1993-12-15 1995-06-22 Silicon Graphics Inc. Superscalar microprocessor instruction pipeline including instruction dispatch and release control
US5974534A (en) * 1994-02-14 1999-10-26 Hewlett-Packard Company Predecoding and steering mechanism for instructions in a superscalar processor
US5682491A (en) * 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US5742784A (en) * 1995-01-25 1998-04-21 International Business Machines Corporation System for reordering of instructions before placement into cache to reduce dispatch latency
WO1997027536A1 (en) * 1996-01-24 1997-07-31 Sun Microsystems, Inc. Instruction folding for a stack-based machine
DE69734399D1 (de) * 1996-01-24 2006-03-02 Sun Microsystems Inc Verfahren und vorrichtung zur stapel-cachespeicherung
JPH1011289A (ja) * 1996-06-19 1998-01-16 Mitsubishi Electric Corp 並列処理プロセッサにおける命令数拡張方法および並列処理プロセッサ
US5870578A (en) * 1997-12-09 1999-02-09 Advanced Micro Devices, Inc. Workload balancing in a microprocessor for reduced instruction dispatch stalling
FR2793572B1 (fr) * 1999-05-10 2001-10-05 Cit Alcatel Procede et dispositif pour commander l'ordre de depart d'informations ou d'objets stockes temporairement
JP2001034474A (ja) * 1999-07-16 2001-02-09 Nec Corp データ処理装置及びデータ処理方法
US7711926B2 (en) 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US6826681B2 (en) 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
GB2437836B (en) * 2005-02-25 2009-01-14 Clearspeed Technology Plc Microprocessor architectures
US20060200648A1 (en) * 2005-03-02 2006-09-07 Andreas Falkenberg High-level language processor apparatus and method
JP2010097557A (ja) * 2008-10-20 2010-04-30 Toshiba Corp セットアソシアティブ方式のキャッシュ装置及びキャッシュ方法
JP5300407B2 (ja) 2008-10-20 2013-09-25 株式会社東芝 仮想アドレスキャッシュメモリ及び仮想アドレスキャッシュ方法
JP2011198091A (ja) 2010-03-19 2011-10-06 Toshiba Corp 仮想アドレスキャッシュメモリ、プロセッサ及びマルチプロセッサシステム
US10824927B1 (en) * 2018-09-21 2020-11-03 Enernet Global, LLC Systems, methods and computer readable medium for management of data buffers using functional paradigm

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437149A (en) * 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
EP0239081B1 (de) * 1986-03-26 1995-09-06 Hitachi, Ltd. Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
US4916652A (en) * 1987-09-30 1990-04-10 International Business Machines Corporation Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures
US5027270A (en) * 1988-10-11 1991-06-25 Mips Computer Systems, Inc. Processor controlled interface with instruction streaming
US5099421A (en) * 1988-12-30 1992-03-24 International Business Machine Corporation Variable length pipe operations sequencing
US5075844A (en) * 1989-05-24 1991-12-24 Tandem Computers Incorporated Paired instruction processor precise exception handling mechanism
US5197135A (en) * 1990-06-26 1993-03-23 International Business Machines Corporation Memory management for scalable compound instruction set machines with in-memory compounding

Also Published As

Publication number Publication date
EP0449661A2 (de) 1991-10-02
EP0449661A3 (en) 1992-06-03
DE69114333T2 (de) 1996-05-15
JP2818249B2 (ja) 1998-10-30
EP0449661B1 (de) 1995-11-08
JPH03282958A (ja) 1991-12-13
US5377339A (en) 1994-12-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee