DE69114786D1 - Verfahren zum ätzen von mindestens einer vertiefung in einem substrat und dadurch erhaltenes substrat. - Google Patents

Verfahren zum ätzen von mindestens einer vertiefung in einem substrat und dadurch erhaltenes substrat.

Info

Publication number
DE69114786D1
DE69114786D1 DE69114786T DE69114786T DE69114786D1 DE 69114786 D1 DE69114786 D1 DE 69114786D1 DE 69114786 T DE69114786 T DE 69114786T DE 69114786 T DE69114786 T DE 69114786T DE 69114786 D1 DE69114786 D1 DE 69114786D1
Authority
DE
Germany
Prior art keywords
etching
substrate
pct
depth
cavities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69114786T
Other languages
English (en)
Other versions
DE69114786T2 (de
Inventor
Lintel Harald Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Westonbridge International Ltd
Original Assignee
Westonbridge International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westonbridge International Ltd filed Critical Westonbridge International Ltd
Application granted granted Critical
Publication of DE69114786D1 publication Critical patent/DE69114786D1/de
Publication of DE69114786T2 publication Critical patent/DE69114786T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H1/00—Contacts
    • H01H1/0036—Switches making use of microelectromechanical systems [MEMS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Micromachines (AREA)
  • Particle Formation And Scattering Control In Inkjet Printers (AREA)
  • ing And Chemical Polishing (AREA)
  • Magnetic Heads (AREA)
DE69114786T 1990-03-16 1991-03-07 Verfahren zum ätzen von mindestens einer vertiefung in einem substrat und dadurch erhaltenes substrat. Expired - Fee Related DE69114786T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH872/90A CH682528A5 (fr) 1990-03-16 1990-03-16 Procédé de réalisation par attaque chimique d'au moins une cavité dans un substrat et substrat obtenu par ce procédé.
PCT/EP1991/000426 WO1991014281A1 (en) 1990-03-16 1991-03-07 Etching method for obtaining at least one cavity in a substrate and substrate obtained by such method

Publications (2)

Publication Number Publication Date
DE69114786D1 true DE69114786D1 (de) 1996-01-04
DE69114786T2 DE69114786T2 (de) 1996-05-23

Family

ID=4197137

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114786T Expired - Fee Related DE69114786T2 (de) 1990-03-16 1991-03-07 Verfahren zum ätzen von mindestens einer vertiefung in einem substrat und dadurch erhaltenes substrat.

Country Status (10)

Country Link
US (1) US5316618A (de)
EP (1) EP0472702B1 (de)
JP (1) JPH04506727A (de)
AT (1) ATE130703T1 (de)
AU (1) AU7475491A (de)
CA (1) CA2053859A1 (de)
CH (1) CH682528A5 (de)
DE (1) DE69114786T2 (de)
ES (1) ES2080304T3 (de)
WO (1) WO1991014281A1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03292744A (ja) * 1990-01-24 1991-12-24 Toshiba Corp 化合物半導体装置およびその製造方法
DE4340590A1 (de) * 1992-12-03 1994-06-09 Hewlett Packard Co Grabenisolation unter Verwendung dotierter Seitenwände
JP3205103B2 (ja) * 1993-01-07 2001-09-04 松下電器産業株式会社 半導体装置の製造方法
US5436201A (en) * 1993-05-28 1995-07-25 Hughes Aircraft Company Dual etchant process, particularly for gate recess fabrication in GaAs MMIC chips
US5632908A (en) * 1995-02-01 1997-05-27 Lucent Technologies Inc. Method for making aligned features
US5632854A (en) * 1995-08-21 1997-05-27 Motorola, Inc. Pressure sensor method of fabrication
JP3734586B2 (ja) * 1997-03-05 2006-01-11 富士通株式会社 半導体装置及びその製造方法
DE19719862A1 (de) * 1997-05-12 1998-11-19 Fraunhofer Ges Forschung Mikromembranpumpe
US6623579B1 (en) * 1999-11-02 2003-09-23 Alien Technology Corporation Methods and apparatus for fluidic self assembly
US6479395B1 (en) * 1999-11-02 2002-11-12 Alien Technology Corporation Methods for forming openings in a substrate and apparatuses with these openings and methods for creating assemblies with openings
TW480621B (en) * 2001-03-02 2002-03-21 Acer Comm & Multimedia Inc Method for producing high density chip
US20040073175A1 (en) * 2002-01-07 2004-04-15 Jacobson James D. Infusion system
AU2005211226A1 (en) * 2004-02-06 2005-08-18 Karmic, Sarl Microreplication of transitory-image relief pattern based optically variable devices
US8070971B2 (en) * 2004-06-04 2011-12-06 Nxp B.V. Etch method
US7452748B1 (en) 2004-11-08 2008-11-18 Alien Technology Corporation Strap assembly comprising functional block deposited therein and method of making same
FR2901635A1 (fr) * 2006-06-09 2007-11-30 Commissariat Energie Atomique Dispositif de connexion tridimensionnel dans un substrat
US8132775B2 (en) * 2008-04-29 2012-03-13 International Business Machines Corporation Solder mold plates used in packaging process and method of manufacturing solder mold plates
FR2985602B1 (fr) * 2012-01-05 2014-03-07 Commissariat Energie Atomique Procede de gravure d'un motif complexe
US9005463B2 (en) * 2013-05-29 2015-04-14 Micron Technology, Inc. Methods of forming a substrate opening

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3844858A (en) * 1968-12-31 1974-10-29 Texas Instruments Inc Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate
JPS5898927A (ja) * 1981-12-09 1983-06-13 Hitachi Ltd シリコン基板のエツチング方法
DE3225206C1 (de) * 1982-07-06 1983-10-27 Dr. Johannes Heidenhain Gmbh, 8225 Traunreut Verfahren zum einseitigen Ätzen von Platten
US4761210A (en) * 1985-09-30 1988-08-02 Siemens Aktiengesellschaft Method for generating structures in micro-mechanics
JP2514210B2 (ja) * 1987-07-23 1996-07-10 日産自動車株式会社 半導体基板のエッチング方法
US5024953A (en) * 1988-03-22 1991-06-18 Hitachi, Ltd. Method for producing opto-electric transducing element
US4899178A (en) * 1989-02-02 1990-02-06 Xerox Corporation Thermal ink jet printhead with internally fed ink reservoir
US4957592A (en) * 1989-12-27 1990-09-18 Xerox Corporation Method of using erodable masks to produce partially etched structures in ODE wafer structures

Also Published As

Publication number Publication date
CA2053859A1 (en) 1991-09-17
CH682528A5 (fr) 1993-09-30
DE69114786T2 (de) 1996-05-23
ES2080304T3 (es) 1996-02-01
WO1991014281A1 (en) 1991-09-19
ATE130703T1 (de) 1995-12-15
AU7475491A (en) 1991-10-10
JPH04506727A (ja) 1992-11-19
EP0472702A1 (de) 1992-03-04
US5316618A (en) 1994-05-31
EP0472702B1 (de) 1995-11-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee