DE69120483D1 - Halbleiter-Speicher mit unterdrücktem Testmodus-Eingang während des Strom-Einschaltens - Google Patents
Halbleiter-Speicher mit unterdrücktem Testmodus-Eingang während des Strom-EinschaltensInfo
- Publication number
- DE69120483D1 DE69120483D1 DE69120483T DE69120483T DE69120483D1 DE 69120483 D1 DE69120483 D1 DE 69120483D1 DE 69120483 T DE69120483 T DE 69120483T DE 69120483 T DE69120483 T DE 69120483T DE 69120483 D1 DE69120483 D1 DE 69120483D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- test mode
- during power
- input during
- mode input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US57014890A | 1990-08-17 | 1990-08-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69120483D1 true DE69120483D1 (de) | 1996-08-01 |
| DE69120483T2 DE69120483T2 (de) | 1996-11-14 |
Family
ID=24278453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69120483T Expired - Fee Related DE69120483T2 (de) | 1990-08-17 | 1991-08-12 | Halbleiter-Speicher mit unterdrücktem Testmodus-Eingang während des Strom-Einschaltens |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5408435A (de) |
| EP (1) | EP0475588B1 (de) |
| JP (1) | JP3012710B2 (de) |
| KR (1) | KR100205449B1 (de) |
| DE (1) | DE69120483T2 (de) |
Families Citing this family (64)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5781753A (en) * | 1989-02-24 | 1998-07-14 | Advanced Micro Devices, Inc. | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions |
| US5299203A (en) | 1990-08-17 | 1994-03-29 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with a flag for indicating test mode |
| US5072138A (en) | 1990-08-17 | 1991-12-10 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with sequential clocked access codes for test mode entry |
| US5473571A (en) * | 1993-09-30 | 1995-12-05 | Nippon Telegraph And Telephone Corporation | Data hold circuit |
| JP3526898B2 (ja) * | 1993-12-28 | 2004-05-17 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US5526311A (en) * | 1993-12-30 | 1996-06-11 | Intel Corporation | Method and circuitry for enabling and permanently disabling test mode access in a flash memory device |
| JP3380978B2 (ja) * | 1994-12-15 | 2003-02-24 | 三菱電機株式会社 | 半導体装置 |
| KR0120606B1 (ko) * | 1994-12-31 | 1997-10-30 | 김주용 | 반도체 기억소자의 자동모드 선택 회로 |
| US5557579A (en) * | 1995-06-26 | 1996-09-17 | Micron Technology, Inc. | Power-up circuit responsive to supply voltage transients with signal delay |
| US5627478A (en) * | 1995-07-06 | 1997-05-06 | Micron Technology, Inc. | Apparatus for disabling and re-enabling access to IC test functions |
| US5657293A (en) * | 1995-08-23 | 1997-08-12 | Micron Technology, Inc. | Integrated circuit memory with back end mode disable |
| US5659508A (en) * | 1995-12-06 | 1997-08-19 | International Business Machine Corporation | Special mode enable transparent to normal mode operation |
| KR0179793B1 (ko) * | 1995-12-28 | 1999-04-15 | 문정환 | 반도체 메모리의 센스 앰프 출력 제어 회로 |
| US5619466A (en) * | 1996-01-19 | 1997-04-08 | Sgs-Thomson Microelectronics, Inc. | Low-power read circuit and method for controlling a sense amplifier |
| US5802004A (en) * | 1996-01-19 | 1998-09-01 | Sgs-Thomson Microelectronics, Inc. | Clocked sense amplifier with wordline tracking |
| US5745432A (en) * | 1996-01-19 | 1998-04-28 | Sgs-Thomson Microelectronics, Inc. | Write driver having a test function |
| US5848018A (en) * | 1996-01-19 | 1998-12-08 | Stmicroelectronics, Inc. | Memory-row selector having a test function |
| US5883838A (en) * | 1996-01-19 | 1999-03-16 | Stmicroelectronics, Inc. | Device and method for driving a conductive path with a signal |
| US5845059A (en) * | 1996-01-19 | 1998-12-01 | Stmicroelectronics, Inc. | Data-input device for generating test signals on bit and bit-complement lines |
| US5691950A (en) * | 1996-01-19 | 1997-11-25 | Sgs-Thomson Microelectronics, Inc. | Device and method for isolating bit lines from a data line |
| US6144594A (en) * | 1996-01-19 | 2000-11-07 | Stmicroelectronics, Inc. | Test mode activation and data override |
| US5793775A (en) * | 1996-01-26 | 1998-08-11 | Micron Quantum Devices, Inc. | Low voltage test mode operation enable scheme with hardware safeguard |
| FR2751461B1 (fr) * | 1996-07-22 | 1998-11-06 | Sgs Thomson Microelectronics | Dispositif de controle de finalite de test |
| US5820519A (en) * | 1996-08-09 | 1998-10-13 | Slenker; Stephen | Bed exercise machine |
| FR2754100B1 (fr) * | 1996-09-30 | 1998-11-20 | Sgs Thomson Microelectronics | Memoire a acces serie avec securisation de l'ecriture |
| IT1286037B1 (it) * | 1996-10-25 | 1998-07-07 | Sgs Thomson Microelectronics | Circuito per la abilitazione selettiva di una pluralita' di alternative circuitali di un circuito integrato |
| US6059450A (en) * | 1996-12-21 | 2000-05-09 | Stmicroelectronics, Inc. | Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device |
| US5883844A (en) * | 1997-05-23 | 1999-03-16 | Stmicroelectronics, Inc. | Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof |
| US5944845A (en) * | 1997-06-26 | 1999-08-31 | Micron Technology, Inc. | Circuit and method to prevent inadvertent test mode entry |
| US5881013A (en) * | 1997-06-27 | 1999-03-09 | Siemens Aktiengesellschaft | Apparatus for controlling circuit response during power-up |
| US5848010A (en) * | 1997-07-14 | 1998-12-08 | Micron Technology, Inc. | Circuit and method for antifuse stress test |
| US5995424A (en) * | 1997-07-16 | 1999-11-30 | Tanisys Technology, Inc. | Synchronous memory test system |
| US6009026A (en) * | 1997-07-28 | 1999-12-28 | International Business Machines Corporation | Compressed input/output test mode |
| US6496027B1 (en) * | 1997-08-21 | 2002-12-17 | Micron Technology, Inc. | System for testing integrated circuit devices |
| JP3204384B2 (ja) * | 1997-12-10 | 2001-09-04 | エヌイーシーマイクロシステム株式会社 | 半導体記憶回路 |
| JP3292145B2 (ja) | 1998-06-26 | 2002-06-17 | 日本電気株式会社 | 半導体記憶装置 |
| JP3802239B2 (ja) * | 1998-08-17 | 2006-07-26 | 株式会社東芝 | 半導体集積回路 |
| KR100283906B1 (ko) * | 1998-10-31 | 2001-03-02 | 김영환 | 반도체 메모리의 초기 안정화 신호 발생 회로 |
| US6060919A (en) * | 1998-12-04 | 2000-05-09 | Ramtron International Corporation | CMOS preferred state power-up latch |
| US6211710B1 (en) * | 1998-12-30 | 2001-04-03 | Texas Instruments India Limited | Circuit for generating a power-up configuration pulse |
| US6651196B1 (en) | 1999-02-16 | 2003-11-18 | Fujitsu Limited | Semiconductor device having test mode entry circuit |
| KR100309465B1 (ko) | 1999-03-29 | 2001-10-29 | 김영환 | 에스램 셀 전원 인가회로 |
| JP2001243797A (ja) * | 2000-02-29 | 2001-09-07 | Fujitsu Ltd | 半導体装置及びその試験方法 |
| JP2001256711A (ja) | 2000-03-14 | 2001-09-21 | Alps Electric Co Ltd | Ｆｄｄ装置用ｉｃのテストモード切換方法およびテストモード切換装置、ｆｄｄ装置 |
| JP3645791B2 (ja) * | 2000-05-29 | 2005-05-11 | エルピーダメモリ株式会社 | 同期型半導体記憶装置 |
| KR100347068B1 (ko) * | 2000-07-20 | 2002-08-03 | 삼성전자 주식회사 | 다른 테스트 모드들에서 동작 가능한 반도체 집적 회로메모리 장치 |
| US6522589B1 (en) | 2000-09-27 | 2003-02-18 | Kabushiki Kaisha Toshiba | Semiconductor apparatus and mode setting method for semiconductor apparatus |
| US6944784B2 (en) * | 2001-06-29 | 2005-09-13 | Intel Corporation | Flip-flop having multiple clock sources and method therefore |
| KR100528164B1 (ko) * | 2004-02-13 | 2005-11-15 | 주식회사 하이닉스반도체 | 반도체 기억 소자에서의 온 다이 터미네이션 모드 전환회로 및 그 방법 |
| US7860172B2 (en) * | 2004-05-13 | 2010-12-28 | International Business Machines Corporation | Self clock generation structure for low power local clock buffering decoder |
| US7213188B2 (en) * | 2004-08-31 | 2007-05-01 | Micron Technology, Inc. | Accessing test modes using command sequences |
| US7584384B2 (en) * | 2004-09-07 | 2009-09-01 | Russell Robert J | Method and apparatus for enabling and disabling a test mode of operation of an electronic memory device without additional interconnects or commands |
| US7557604B2 (en) * | 2005-05-03 | 2009-07-07 | Oki Semiconductor Co., Ltd. | Input circuit for mode setting |
| EP1798626A1 (de) * | 2005-12-13 | 2007-06-20 | Stmicroelectronics Sa | Voltage regulation circuit, in particular for booster pump |
| US7450452B2 (en) * | 2006-06-23 | 2008-11-11 | Texas Instruments Incorporated | Method to identify or screen VMIN drift on memory cells during burn-in or operation |
| US7945827B1 (en) * | 2006-12-28 | 2011-05-17 | Marvell International Technology Ltd. | Method and device for scan chain management of dies reused in a multi-chip package |
| KR100851994B1 (ko) | 2007-02-12 | 2008-08-13 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 이를 이용한 반도체 집적 회로 |
| US7893716B1 (en) * | 2007-05-11 | 2011-02-22 | Altera Corporation | Hotsocket detection circuitry |
| US7937631B2 (en) * | 2007-08-28 | 2011-05-03 | Qimonda Ag | Method for self-test and self-repair in a multi-chip package environment |
| JP5195393B2 (ja) * | 2008-12-19 | 2013-05-08 | 富士通セミコンダクター株式会社 | 半導体メモリ、半導体メモリの製造方法および半導体メモリの試験方法 |
| US9506979B2 (en) | 2014-04-02 | 2016-11-29 | Freescale Semiconductor, Inc. | Test mode entry interlock |
| US10043563B2 (en) * | 2014-10-15 | 2018-08-07 | Agency For Science, Technology And Research | Flip-flop circuit, method of controlling a flip-flop circuit and memory device |
| US11144104B2 (en) * | 2020-02-14 | 2021-10-12 | Silicon Laboratories Inc. | Mode selection circuit for low-cost integrated circuits such as microcontrollers |
| CN112986797A (zh) * | 2021-02-08 | 2021-06-18 | 昂宝电子（上海）有限公司 | 芯片测试电路及方法 |
Family Cites Families (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4104734A (en) * | 1977-06-30 | 1978-08-01 | Fairchild Camera And Instrument Corporation | Low voltage data retention bias circuitry for volatile memories |
| US4148099A (en) * | 1978-04-11 | 1979-04-03 | Ncr Corporation | Memory device having a minimum number of pins |
| DE2944149C2 (de) * | 1979-11-02 | 1985-02-21 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Integrierte Schaltungsanordnung in MOS-Technik |
| EP0079885A4 (de) * | 1981-05-27 | 1984-03-01 | Mostek Corp | Stromversorgungssteuereinheit für integrierte schaltung. |
| US4507761A (en) * | 1982-04-20 | 1985-03-26 | Mostek Corporation | Functional command for semiconductor memory |
| JPS5940393A (ja) * | 1982-08-31 | 1984-03-06 | Nec Corp | メモリ回路 |
| JPS5990275A (ja) * | 1982-11-12 | 1984-05-24 | Toshiba Corp | カセツト式記憶装置 |
| JPS59185097A (ja) * | 1983-04-04 | 1984-10-20 | Oki Electric Ind Co Ltd | 自己診断機能付メモリ装置 |
| GB2138230B (en) * | 1983-04-12 | 1986-12-03 | Sony Corp | Dynamic random access memory arrangements |
| US4794559A (en) * | 1984-07-05 | 1988-12-27 | American Telephone And Telegraph Company, At&T Bell Laboratories | Content addressable semiconductor memory arrays |
| US4654849B1 (en) * | 1984-08-31 | 1999-06-22 | Texas Instruments Inc | High speed concurrent testing of dynamic read/write memory array |
| US4777626A (en) * | 1984-12-22 | 1988-10-11 | Tokyo Electric Co., Ltd. | Memory device having backup power supply |
| US4755964A (en) * | 1985-04-19 | 1988-07-05 | American Telephone And Telegraph Company | Memory control circuit permitting microcomputer system to utilize static and dynamic rams |
| JPS61247984A (ja) * | 1985-04-26 | 1986-11-05 | Toshiba Corp | テスト回路 |
| JPS61292755A (ja) * | 1985-06-20 | 1986-12-23 | Fujitsu Ltd | 半導体集積回路 |
| GB8518859D0 (en) * | 1985-07-25 | 1985-08-29 | Int Computers Ltd | Digital integrated circuits |
| JPS62170094A (ja) * | 1986-01-21 | 1987-07-27 | Mitsubishi Electric Corp | 半導体記憶回路 |
| JPS6337269A (ja) * | 1986-08-01 | 1988-02-17 | Fujitsu Ltd | モ−ド選定回路 |
| US5001670A (en) * | 1987-02-06 | 1991-03-19 | Tektronix, Inc. | Nonvolatile memory protection |
| JP2603206B2 (ja) * | 1987-03-16 | 1997-04-23 | シーメンス、アクチエンゲゼルシヤフト | 多段集積デコーダ装置 |
| US4812675A (en) * | 1987-04-15 | 1989-03-14 | Exel Microelectronics Incorporated | Security element circuit for programmable logic array |
| JPS6427094A (en) * | 1987-07-23 | 1989-01-30 | Mitsubishi Electric Corp | Mos-type semiconductor memory |
| JP2521774B2 (ja) * | 1987-10-02 | 1996-08-07 | 株式会社日立製作所 | メモリ内蔵型論理ｌｓｉ及びそのｌｓｉの試験方法 |
| JPH01100793A (ja) * | 1987-10-13 | 1989-04-19 | Nec Corp | Ｃｍｏｓ型半導体メモリ回路 |
| JPH081760B2 (ja) * | 1987-11-17 | 1996-01-10 | 三菱電機株式会社 | 半導体記憶装置 |
| FR2623652A1 (fr) * | 1987-11-20 | 1989-05-26 | Philips Nv | Unite de memoire statique a plusieurs modes de test et ordinateur muni de telles unites |
| KR900008554B1 (ko) * | 1988-04-23 | 1990-11-24 | 삼성전자 주식회사 | 메모리 동작모드 선택회로 |
| US4987325A (en) * | 1988-07-13 | 1991-01-22 | Samsung Electronics Co., Ltd. | Mode selecting circuit for semiconductor memory device |
| KR910005615B1 (ko) * | 1988-07-18 | 1991-07-31 | 삼성전자 주식회사 | 프로그래머블 순차코오드 인식회로 |
| JPH0697429B2 (ja) * | 1988-11-21 | 1994-11-30 | 日本モトローラ株式会社 | 低電圧阻止制御装置 |
| KR910006241B1 (ko) * | 1988-12-14 | 1991-08-17 | 삼성전자 주식회사 | 복수 테스트모드 선택회로 |
| US4942319A (en) * | 1989-01-19 | 1990-07-17 | National Semiconductor Corp. | Multiple page programmable logic architecture |
| US5019772A (en) * | 1989-05-23 | 1991-05-28 | International Business Machines Corporation | Test selection techniques |
| US5036495A (en) * | 1989-12-28 | 1991-07-30 | International Business Machines Corp. | Multiple mode-set for IC chip |
| US5016219A (en) * | 1990-02-12 | 1991-05-14 | Vlsi Technology, Inc. | Computer memory write protection circuit |
| US4975883A (en) * | 1990-03-29 | 1990-12-04 | Intel Corporation | Method and apparatus for preventing the erasure and programming of a nonvolatile memory |
| US5130645A (en) * | 1990-08-13 | 1992-07-14 | Vlsi Technology, Inc. | Integrated circuit built-in self-test structure |
| US5072138A (en) * | 1990-08-17 | 1991-12-10 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with sequential clocked access codes for test mode entry |
-
1991
- 1991-08-12 DE DE69120483T patent/DE69120483T2/de not_active Expired - Fee Related
- 1991-08-12 EP EP91307419A patent/EP0475588B1/de not_active Expired - Lifetime
- 1991-08-16 KR KR1019910014247A patent/KR100205449B1/ko not_active IP Right Cessation
- 1991-08-16 JP JP3205887A patent/JP3012710B2/ja not_active Expired - Fee Related
-
1992
- 1992-11-20 US US07/984,233 patent/US5408435A/en not_active Expired - Lifetime
-
1995
- 1995-04-18 US US08/424,722 patent/US5706232A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5408435A (en) | 1995-04-18 |
| KR100205449B1 (ko) | 1999-07-01 |
| KR920005170A (ko) | 1992-03-28 |
| EP0475588B1 (de) | 1996-06-26 |
| JPH05274898A (ja) | 1993-10-22 |
| US5706232A (en) | 1998-01-06 |
| DE69120483T2 (de) | 1996-11-14 |
| JP3012710B2 (ja) | 2000-02-28 |
| EP0475588A1 (de) | 1992-03-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |