DE69121501D1 - Mehrschichtige Leiterplatte und Verfahren zu ihrer Herstellung - Google Patents
Mehrschichtige Leiterplatte und Verfahren zu ihrer HerstellungInfo
- Publication number
- DE69121501D1 DE69121501D1 DE69121501T DE69121501T DE69121501D1 DE 69121501 D1 DE69121501 D1 DE 69121501D1 DE 69121501 T DE69121501 T DE 69121501T DE 69121501 T DE69121501 T DE 69121501T DE 69121501 D1 DE69121501 D1 DE 69121501D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacture
- circuit board
- printed circuit
- multilayer printed
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Revoked
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
- H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1438—Treating holes after another process, e.g. coating holes after coating the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1581—Treating the backside of the PCB, e.g. for heating during soldering or providing a liquid coating on the backside
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2255464A JP2739726B2 (ja) | 1990-09-27 | 1990-09-27 | 多層プリント回路板 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69121501D1 true DE69121501D1 (de) | 1996-09-26 |
DE69121501T2 DE69121501T2 (de) | 1997-02-06 |
Family
ID=17279130
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69121501T Revoked DE69121501T2 (de) | 1990-09-27 | 1991-09-25 | Mehrschichtige Leiterplatte und Verfahren zu ihrer Herstellung |
Country Status (4)
Country | Link |
---|---|
US (2) | US5451721A (de) |
EP (1) | EP0478313B1 (de) |
JP (1) | JP2739726B2 (de) |
DE (1) | DE69121501T2 (de) |
Families Citing this family (139)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2739726B2 (ja) | 1990-09-27 | 1998-04-15 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | 多層プリント回路板 |
US5517758A (en) * | 1992-05-29 | 1996-05-21 | Matsushita Electric Industrial Co., Ltd. | Plating method and method for producing a multi-layered printed wiring board using the same |
US5532105A (en) * | 1992-08-07 | 1996-07-02 | Hitachi Chemical Company, Ltd. | Photolithographically viahole-forming photosensitive element comprising two photosensitive layers for the fabrication process of multilayer wiring board |
US5480048A (en) * | 1992-09-04 | 1996-01-02 | Hitachi, Ltd. | Multilayer wiring board fabricating method |
DE69303684T2 (de) * | 1992-09-29 | 1996-11-28 | Matsushita Electric Ind Co Ltd | Verfahren zur Herstellung einer mehrschichtigen Leiterplatte |
JPH06169175A (ja) * | 1992-11-30 | 1994-06-14 | Nec Corp | 多層印刷配線板及びその製造方法 |
DE59208900D1 (de) * | 1992-12-12 | 1997-10-16 | Ibm | Leiterplatten mit lokal erhöhter Verdrahtungsdichte und Herstellungsverfahren für solche Leiterplatten |
DE59208335D1 (de) * | 1992-12-14 | 1997-05-15 | Ibm | Leiterplatten mit lokal erhöhter Verdrahtungsdichte und konischen Bohrungen sowie Herstellungsverfahren für solche Leiterplatten |
US5597983A (en) * | 1994-02-03 | 1997-01-28 | Sgs-Thomson Microelectronics, Inc. | Process of removing polymers in semiconductor vias |
DE4422669A1 (de) * | 1994-06-30 | 1996-01-04 | Siemens Ag | Mehrlagen-Leiterplatte |
JP3121213B2 (ja) * | 1994-07-27 | 2000-12-25 | 株式会社日立製作所 | 感光性樹脂組成物 |
JP3592827B2 (ja) * | 1996-03-06 | 2004-11-24 | 富士写真フイルム株式会社 | 感光性エレメント及び多層配線基板の製造方法 |
DE19612760C2 (de) * | 1996-03-29 | 2002-01-10 | Oce Printing Systems Gmbh | Trägerplatte und Druckkopf mit dieser Trägerplatte |
US5822856A (en) * | 1996-06-28 | 1998-10-20 | International Business Machines Corporation | Manufacturing circuit board assemblies having filled vias |
EP0824301A3 (de) * | 1996-08-09 | 1999-08-11 | Hitachi, Ltd. | Gedruckte Schaltungsplatte, Chipkarte, und Verfahren zu deren Herstellung |
US5981880A (en) * | 1996-08-20 | 1999-11-09 | International Business Machines Corporation | Electronic device packages having glass free non conductive layers |
US6074728A (en) * | 1996-09-11 | 2000-06-13 | Samsung Aerospace Industries, Ltd. | Multi-layered circuit substrate |
US5955192A (en) * | 1996-11-20 | 1999-09-21 | Shin-Etsu Chemical Co., Ltd. | Conductive circuit board and method for making |
US6105243A (en) * | 1996-12-05 | 2000-08-22 | International Business Machines, Corp. | Method of fabricating multilayer printed circuit board |
US6820330B1 (en) * | 1996-12-13 | 2004-11-23 | Tessera, Inc. | Method for forming a multi-layer circuit assembly |
ID19337A (id) | 1996-12-26 | 1998-07-02 | Ajinomoto Kk | Film perekat antar-pelapis untuk papan pembuat kabel cetakan berlapis-banyak dan papan kabel cetakan berlapis-banyak memakai film ini |
US5990421A (en) * | 1997-02-18 | 1999-11-23 | Intel Corporation | Built in board resistors |
US6255039B1 (en) | 1997-04-16 | 2001-07-03 | Isola Laminate Systems Corp. | Fabrication of high density multilayer interconnect printed circuit boards |
US6162997A (en) * | 1997-06-03 | 2000-12-19 | International Business Machines Corporation | Circuit board with primary and secondary through holes |
DE19729587A1 (de) * | 1997-07-10 | 1999-01-14 | Siemens Ag | Verfahren zum Aufbringen von Lot auf Anschlußflächen einer Leiterplatte, Verfahren zur Herstellung eines mit Lot beschichteten Trägers für ein derartiges Verfahren sowie ein derartiger Träger |
US6141870A (en) | 1997-08-04 | 2000-11-07 | Peter K. Trzyna | Method for making electrical device |
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CN100521883C (zh) * | 1997-12-11 | 2009-07-29 | 伊比登株式会社 | 多层印刷电路板的制造方法 |
US6462107B1 (en) | 1997-12-23 | 2002-10-08 | The Texas A&M University System | Photoimageable compositions and films for printed wiring board manufacture |
US6606286B1 (en) | 1998-01-05 | 2003-08-12 | Mitburri Electric Co., Ltd | Tln signal generating apparatus used in optical disc drive and optical disc drive equipped with the apparatus, and optical disc drive equipped with amplitude adjusting apparatus for tracking error signal |
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US6085415A (en) * | 1998-07-27 | 2000-07-11 | Ormet Corporation | Methods to produce insulated conductive through-features in core materials for electric packaging |
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KR100642167B1 (ko) | 1998-09-18 | 2006-11-02 | 훈츠만 어드밴스트 머티리얼스(스위처랜드)게엠베하 | 다층 회로의 제조방법 |
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US6181004B1 (en) | 1999-01-22 | 2001-01-30 | Jerry D. Koontz | Digital signal processing assembly and test method |
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JP3617388B2 (ja) * | 1999-10-20 | 2005-02-02 | 日本電気株式会社 | プリント配線板及びその製造方法 |
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JP2001237512A (ja) * | 1999-12-14 | 2001-08-31 | Nitto Denko Corp | 両面回路基板およびこれを用いた多層配線基板ならびに両面回路基板の製造方法 |
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JP2001274537A (ja) * | 2000-03-28 | 2001-10-05 | Ngk Spark Plug Co Ltd | 配線基板及び配線基板の製造方法 |
JP2001284783A (ja) * | 2000-03-30 | 2001-10-12 | Shinko Electric Ind Co Ltd | 表面実装用基板及び表面実装構造 |
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JP4034046B2 (ja) * | 2001-06-07 | 2008-01-16 | 日本碍子株式会社 | 高精度な貫通孔を有する多層板、及び、回路基板 |
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JP3461172B2 (ja) * | 2001-07-05 | 2003-10-27 | 日東電工株式会社 | 多層配線回路基板の製造方法 |
JP2003023248A (ja) * | 2001-07-05 | 2003-01-24 | Nitto Denko Corp | 多層フレキシブル配線回路基板およびその製造方法 |
TWI312166B (en) | 2001-09-28 | 2009-07-11 | Toppan Printing Co Ltd | Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board |
TWI286826B (en) * | 2001-12-28 | 2007-09-11 | Via Tech Inc | Semiconductor package substrate and process thereof |
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-
1990
- 1990-09-27 JP JP2255464A patent/JP2739726B2/ja not_active Expired - Lifetime
-
1991
- 1991-09-24 US US07/764,733 patent/US5451721A/en not_active Expired - Lifetime
- 1991-09-25 DE DE69121501T patent/DE69121501T2/de not_active Revoked
- 1991-09-25 EP EP91308756A patent/EP0478313B1/de not_active Revoked
-
1995
- 1995-06-30 US US08/497,614 patent/US6378201B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2739726B2 (ja) | 1998-04-15 |
EP0478313B1 (de) | 1996-08-21 |
EP0478313A3 (en) | 1993-01-27 |
DE69121501T2 (de) | 1997-02-06 |
US6378201B1 (en) | 2002-04-30 |
US5451721A (en) | 1995-09-19 |
JPH04148590A (ja) | 1992-05-21 |
EP0478313A2 (de) | 1992-04-01 |
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