DE69123372D1 - Dynamischer RAM mit On-Chip-Fehlerprüfung- und -korrektur und mit optimisierender Bit- und Wortredundanz - Google Patents

Dynamischer RAM mit On-Chip-Fehlerprüfung- und -korrektur und mit optimisierender Bit- und Wortredundanz

Info

Publication number
DE69123372D1
DE69123372D1 DE69123372T DE69123372T DE69123372D1 DE 69123372 D1 DE69123372 D1 DE 69123372D1 DE 69123372 T DE69123372 T DE 69123372T DE 69123372 T DE69123372 T DE 69123372T DE 69123372 D1 DE69123372 D1 DE 69123372D1
Authority
DE
Germany
Prior art keywords
bit
ecc
ecw
chip
redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69123372T
Other languages
English (en)
Inventor
John Edward Barth
Charles Edward Drake
John Atkinson Fifield
William Paul Hovis
Howard Leo Kalter
Scott Clarence Lewis
Daniel John Nickel
Charles Henri Stapper
James Andrew Yankosky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69123372D1 publication Critical patent/DE69123372D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
DE69123372T 1990-02-13 1991-01-24 Dynamischer RAM mit On-Chip-Fehlerprüfung- und -korrektur und mit optimisierender Bit- und Wortredundanz Expired - Lifetime DE69123372D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/479,145 US5134616A (en) 1990-02-13 1990-02-13 Dynamic ram with on-chip ecc and optimized bit and word redundancy

Publications (1)

Publication Number Publication Date
DE69123372D1 true DE69123372D1 (de) 1997-01-16

Family

ID=23902828

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69123372T Expired - Lifetime DE69123372D1 (de) 1990-02-13 1991-01-24 Dynamischer RAM mit On-Chip-Fehlerprüfung- und -korrektur und mit optimisierender Bit- und Wortredundanz

Country Status (10)

Country Link
US (1) US5134616A (de)
EP (1) EP0442301B1 (de)
JP (1) JP2539950B2 (de)
KR (1) KR950011728B1 (de)
AU (1) AU6995891A (de)
CA (1) CA2034027C (de)
DE (1) DE69123372D1 (de)
HK (1) HK62097A (de)
MY (1) MY105290A (de)
SG (1) SG43875A1 (de)

Families Citing this family (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69034227T2 (de) * 1989-04-13 2007-05-03 Sandisk Corp., Sunnyvale EEprom-System mit Blocklöschung
US7190617B1 (en) 1989-04-13 2007-03-13 Sandisk Corporation Flash EEprom system
US5535328A (en) * 1989-04-13 1996-07-09 Sandisk Corporation Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells
GB9007790D0 (en) 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
DE69124285T2 (de) * 1990-05-18 1997-08-14 Fujitsu Ltd Datenverarbeitungssystem mit einem Eingangs-/Ausgangswegetrennmechanismus und Verfahren zur Steuerung des Datenverarbeitungssystems
EP0502207B1 (de) * 1990-09-20 1997-08-27 Fujitsu Limited Eingang-ausgangsteuerungseinrichtung
US5278847A (en) * 1990-12-28 1994-01-11 General Electric Company Fault-tolerant memory system with graceful degradation
EP0514664A3 (en) * 1991-05-20 1993-05-26 International Business Machines Corporation Dynamic random access memory with a redundancy decoder
EP0895162A3 (de) 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Verbesserte DRAM mit eingebauten Registern
JP2922060B2 (ja) * 1992-07-27 1999-07-19 富士通株式会社 半導体記憶装置
KR950008789B1 (ko) * 1992-07-30 1995-08-08 삼성전자주식회사 멀티-이씨씨(ecc)회로를 내장하는 반도체 메모리 장치
US5327548A (en) * 1992-11-09 1994-07-05 International Business Machines Corporation Apparatus and method for steering spare bit in a multiple processor system having a global/local memory architecture
US5742544A (en) * 1994-04-11 1998-04-21 Mosaid Technologies Incorporated Wide databus architecture
US5535226A (en) * 1994-05-31 1996-07-09 International Business Machines Corporation On-chip ECC status
JP3272903B2 (ja) * 1995-03-16 2002-04-08 株式会社東芝 誤り訂正検出回路と半導体記憶装置
US5631868A (en) * 1995-11-28 1997-05-20 International Business Machines Corporation Method and apparatus for testing redundant word and bit lines in a memory array
JPH09245472A (ja) * 1996-03-08 1997-09-19 Mitsubishi Electric Corp メモリカード
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
KR100407349B1 (ko) * 1996-06-29 2004-04-14 삼성전자주식회사 교환기의 화일전송 장치 및 방법
US5708613A (en) * 1996-07-22 1998-01-13 International Business Machines Corporation High performance redundancy in an integrated memory system
US5784391A (en) * 1996-10-08 1998-07-21 International Business Machines Corporation Distributed memory system with ECC and method of operation
DE19647159A1 (de) * 1996-11-14 1998-06-04 Siemens Ag Verfahren zum Testen eines in Zellenfelder unterteilten Speicherchips im laufenden Betrieb eines Rechners unter Einhaltung von Echtzeitbedingungen
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US5691946A (en) * 1996-12-03 1997-11-25 International Business Machines Corporation Row redundancy block architecture
US6032264A (en) * 1997-04-22 2000-02-29 Micron Technology, Inc. Apparatus and method implementing repairs on a memory device
US6058052A (en) * 1997-08-21 2000-05-02 Cypress Semiconductor Corp. Redundancy scheme providing improvements in redundant circuit access time and integrated circuit layout area
KR19990070729A (ko) * 1998-02-24 1999-09-15 김영환 서버/클라이언트 구조를 이용한 홈위치등록기의 인터페이싱 방법
US5963481A (en) * 1998-06-30 1999-10-05 Enhanced Memory Systems, Inc. Embedded enhanced DRAM, and associated method
US6246615B1 (en) * 1998-12-23 2001-06-12 Micron Technology, Inc. Redundancy mapping in a multichip semiconductor package
US6330636B1 (en) 1999-01-29 2001-12-11 Enhanced Memory Systems, Inc. Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank
US6574746B1 (en) * 1999-07-02 2003-06-03 Sun Microsystems, Inc. System and method for improving multi-bit error protection in computer memory systems
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
US6574763B1 (en) 1999-12-28 2003-06-03 International Business Machines Corporation Method and apparatus for semiconductor integrated circuit testing and burn-in
US6791157B1 (en) * 2000-01-18 2004-09-14 Advanced Micro Devices, Inc. Integrated circuit package incorporating programmable elements
US6732266B1 (en) * 2000-08-28 2004-05-04 Advanced Micro Devices, Inc. Method and apparatus for reconfiguring circuit board and integrated circuit packet arrangement with one-time programmable elements
DE10120670B4 (de) * 2001-04-27 2008-08-21 Qimonda Ag Verfahren zur Reparatur von Hardwarefehlern in Speicherbausteinen
CN1518696A (zh) * 2001-06-21 2004-08-04 皇家菲利浦电子有限公司 存储器错误处理方法与电路配置
US20030115538A1 (en) * 2001-12-13 2003-06-19 Micron Technology, Inc. Error correction in ROM embedded DRAM
ITMI20020260A1 (it) * 2002-02-12 2003-08-12 Ausimont Spa Dispersioni acquose di fluoropolimeri
US7149941B2 (en) 2002-04-30 2006-12-12 International Business Machines Corporation Optimized ECC/redundancy fault recovery
US7308621B2 (en) 2002-04-30 2007-12-11 International Business Machines Corporation Testing of ECC memories
JP3914839B2 (ja) * 2002-07-11 2007-05-16 エルピーダメモリ株式会社 半導体記憶装置
US6888187B2 (en) 2002-08-26 2005-05-03 International Business Machines Corporation DRAM cell with enhanced SER immunity
US7010741B2 (en) * 2002-10-29 2006-03-07 Mosaid Technologies Method and circuit for error correction in CAM cells
CA2447204C (en) * 2002-11-29 2010-03-23 Memory Management Services Ltd. Error correction scheme for memory
US7131039B2 (en) * 2002-12-11 2006-10-31 Hewlett-Packard Development Company, L.P. Repair techniques for memory with multiple redundancy
US7187602B2 (en) * 2003-06-13 2007-03-06 Infineon Technologies Aktiengesellschaft Reducing memory failures in integrated circuits
US7281177B2 (en) * 2003-07-14 2007-10-09 International Business Machines Corporation Autonomic parity exchange
US7254754B2 (en) * 2003-07-14 2007-08-07 International Business Machines Corporation Raid 3+3
EP1536431A1 (de) * 2003-11-26 2005-06-01 Infineon Technologies AG Anordnung mit einem Speicher zum Speichern von Daten
JP2005203064A (ja) * 2004-01-19 2005-07-28 Toshiba Corp 半導体記憶装置
US7341765B2 (en) * 2004-01-27 2008-03-11 Battelle Energy Alliance, Llc Metallic coatings on silicon substrates, and methods of forming metallic coatings on silicon substrates
KR101013280B1 (ko) * 2004-02-13 2011-02-09 주식회사 케이티 전화망을 통한 분산 이기종 음성인식 자동 교환 시스템에대한 자동 관리 장치 및 그 방법
JP4413091B2 (ja) * 2004-06-29 2010-02-10 株式会社ルネサステクノロジ 半導体装置
JP4802515B2 (ja) * 2005-03-01 2011-10-26 株式会社日立製作所 半導体装置
KR100694407B1 (ko) * 2005-04-21 2007-03-12 주식회사 하이닉스반도체 불량 셀 교정 회로를 포함하는 불휘발성 강유전체 메모리장치
US20060265636A1 (en) * 2005-05-19 2006-11-23 Klaus Hummler Optimized testing of on-chip error correction circuit
US7298171B2 (en) * 2005-07-08 2007-11-20 United Memories, Inc. Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices
US7404136B2 (en) * 2005-07-15 2008-07-22 Infineon Technologies Ag Semiconductor memory device including a signal control device and method of operating the same
KR100669352B1 (ko) * 2005-09-07 2007-01-16 삼성전자주식회사 카피 백 프로그램 동작 동안에 에러 검출 및 데이터 리로딩동작을 수행할 수 있는 낸드 플래시 메모리 장치
JP4768374B2 (ja) * 2005-09-16 2011-09-07 株式会社東芝 半導体記憶装置
KR20070076849A (ko) * 2006-01-20 2007-07-25 삼성전자주식회사 메모리 카드의 카피백 동작을 수행하는 장치 및 방법
JP2007257791A (ja) * 2006-03-24 2007-10-04 Fujitsu Ltd 半導体記憶装置
US8069377B2 (en) 2006-06-26 2011-11-29 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US7774684B2 (en) * 2006-06-30 2010-08-10 Intel Corporation Reliability, availability, and serviceability in a memory device
KR101364443B1 (ko) * 2007-01-31 2014-02-17 삼성전자주식회사 메모리 시스템, 이 시스템을 위한 메모리 제어기와 메모리,이 시스템의 신호 구성 방법
US7840876B2 (en) * 2007-02-20 2010-11-23 Qimonda Ag Power savings for memory with error correction mode
US7499308B2 (en) * 2007-03-21 2009-03-03 International Business Machines Corporation Programmable heavy-ion sensing device for accelerated DRAM soft error detection
US9471418B2 (en) * 2007-06-19 2016-10-18 Samsung Electronics Co., Ltd. Memory system that detects bit errors due to read disturbance and methods thereof
JP4868607B2 (ja) * 2008-01-22 2012-02-01 株式会社リコー Ｓｉｍｄ型マイクロプロセッサ
US20110173577A1 (en) * 2008-02-01 2011-07-14 International Business Machines Corporation Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields
JP2010003348A (ja) * 2008-06-19 2010-01-07 Toshiba Corp 半導体記憶装置及び誤り訂正方法
US20110088008A1 (en) * 2009-10-14 2011-04-14 International Business Machines Corporation Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor
US8458572B1 (en) 2009-11-24 2013-06-04 Apple Inc. Efficient storage of error correction information in DRAM
US8365015B1 (en) 2010-08-09 2013-01-29 Nvidia Corporation Memory-based error recovery
TW201212035A (en) * 2010-09-10 2012-03-16 Jmicron Technology Corp Access method of volatile memory and access apparatus of volatile memory
KR20120076814A (ko) * 2010-12-30 2012-07-10 에스케이하이닉스 주식회사 집적회로 칩, 마스터 칩과 슬레이브 칩을 포함하는 시스템 및 이의 동작방법
US8719648B2 (en) 2011-07-27 2014-05-06 International Business Machines Corporation Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture
US8484543B2 (en) * 2011-08-08 2013-07-09 International Business Machines Corporation Fusebay controller structure, system, and method
US8837240B2 (en) 2011-08-31 2014-09-16 Kabushiki Kaisha Toshiba Semiconductor memory device and defective cell relieving method
JP5481444B2 (ja) * 2011-08-31 2014-04-23 株式会社東芝 半導体装置
US8537627B2 (en) 2011-09-01 2013-09-17 International Business Machines Corporation Determining fusebay storage element usage
KR102143517B1 (ko) 2013-02-26 2020-08-12 삼성전자 주식회사 에러 정정회로를 포함하는 반도체 메모리 장치 및 반도체 메모리 장치의 동작방법
US9430328B2 (en) 2014-01-24 2016-08-30 Stmicroelectronics S.R.L. Error correction in memory devices by multiple readings with different references
US9349490B2 (en) 2014-01-24 2016-05-24 Stmicroelectronics S.R.L. Error correction in differential memory devices with reading in single-ended mode in addition to reading in differential mode
KR102178137B1 (ko) * 2014-08-26 2020-11-12 삼성전자주식회사 반도체 메모리 장치, 이의 에러 정정 방법 및 이를 포함하는 메모리 시스템
US9703632B2 (en) * 2014-11-07 2017-07-11 Nxp B. V. Sleep mode operation for volatile memory circuits
US9692455B2 (en) 2015-09-11 2017-06-27 Micron Technology, Inc. Multi channel memory with flexible code-length ECC
KR20170035103A (ko) 2015-09-22 2017-03-30 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
KR102435181B1 (ko) 2015-11-16 2022-08-23 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 시스템의 동작 방법
FR3044817B1 (fr) * 2015-12-02 2017-12-22 St Microelectronics Rousset Procede de gestion d'une ligne de bits defectueuse du plan memoire d'une memoire non volatile et dispositif de memoire correspondant
KR20180073129A (ko) * 2016-12-22 2018-07-02 에스케이하이닉스 주식회사 에러 정정 코드 회로를 갖는 반도체 메모리 장치
US9905315B1 (en) * 2017-01-24 2018-02-27 Nxp B.V. Error-resilient memory device with row and/or column folding with redundant resources and repair method thereof
US10916324B2 (en) 2018-09-11 2021-02-09 Micron Technology, Inc. Data state synchronization involving memory cells having an inverted data state written thereto
KR102211648B1 (ko) * 2019-03-08 2021-02-03 서울대학교산학협력단 신드롬을 기반으로 한 전자 서명을 통해 데이터 통신이 가능한 전자 장치 및 그 동작 방법
US10998081B1 (en) * 2020-02-14 2021-05-04 Winbond Electronics Corp. Memory storage device having automatic error repair mechanism and method thereof

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3714637A (en) * 1970-09-30 1973-01-30 Ibm Monolithic memory utilizing defective storage cells
US3735368A (en) * 1971-06-25 1973-05-22 Ibm Full capacity monolithic memory utilizing defective storage cells
US3753244A (en) * 1971-08-18 1973-08-14 Ibm Yield enhancement redundancy technique
US3781826A (en) * 1971-11-15 1973-12-25 Ibm Monolithic memory utilizing defective storage cells
US3755791A (en) * 1972-06-01 1973-08-28 Ibm Memory system with temporary or permanent substitution of cells for defective cells
JPS5539073B2 (de) * 1974-12-25 1980-10-08
US4335459A (en) * 1980-05-20 1982-06-15 Miller Richard L Single chip random access memory with increased yield and reliability
JPS5771596A (en) * 1980-10-20 1982-05-04 Fujitsu Ltd Nonolithic memory chip provided with correcting function
US4380066A (en) * 1980-12-04 1983-04-12 Burroughs Corporation Defect tolerant memory
US4493081A (en) * 1981-06-26 1985-01-08 Computer Automation, Inc. Dynamic memory with error correction on refresh
JPS58139399A (ja) * 1982-02-15 1983-08-18 Hitachi Ltd 半導体記憶装置
JPS59231852A (ja) * 1983-06-15 1984-12-26 Hitachi Ltd 半導体装置
JPS6013400A (ja) * 1983-07-01 1985-01-23 Hitachi Micro Comput Eng Ltd 半導体記憶装置
US4570084A (en) * 1983-11-21 1986-02-11 International Business Machines Corporation Clocked differential cascode voltage switch logic systems
DE3582376D1 (de) * 1984-08-03 1991-05-08 Toshiba Kawasaki Kk Halbleiterspeicheranordnung.
JPS6150293A (ja) * 1984-08-17 1986-03-12 Fujitsu Ltd 半導体記憶装置
US4654849B1 (en) * 1984-08-31 1999-06-22 Texas Instruments Inc High speed concurrent testing of dynamic read/write memory array
JPS6199999A (ja) * 1984-10-19 1986-05-19 Hitachi Ltd 半導体記憶装置
JPS61126697A (ja) * 1984-11-22 1986-06-14 Toshiba Corp 半導体記憶装置
JPH0754640B2 (ja) * 1984-11-22 1995-06-07 株式会社東芝 半導体記憶装置の製造方法
US4726021A (en) * 1985-04-17 1988-02-16 Hitachi, Ltd. Semiconductor memory having error correcting means
JPS61264599A (ja) * 1985-05-16 1986-11-22 Fujitsu Ltd 半導体記憶装置
JPS61278100A (ja) * 1985-05-31 1986-12-08 Mitsubishi Electric Corp 半導体記憶装置
JPS61294562A (ja) * 1985-06-21 1986-12-25 Mitsubishi Electric Corp 半導体記憶装置
JPS6318598A (ja) * 1986-07-09 1988-01-26 Nippon Telegr & Teleph Corp <Ntt> 自己訂正半導体メモリ
JPS62250600A (ja) * 1986-04-22 1987-10-31 Sharp Corp 半導体集積回路装置
JPS62293598A (ja) * 1986-06-12 1987-12-21 Toshiba Corp 半導体記憶装置
US4845664A (en) * 1986-09-15 1989-07-04 International Business Machines Corp. On-chip bit reordering structure
US4754433A (en) * 1986-09-16 1988-06-28 Ibm Corporation Dynamic ram having multiplexed twin I/O line pairs
US4801988A (en) * 1986-10-31 1989-01-31 International Business Machines Corporation Semiconductor trench capacitor cell with merged isolation and node trench construction
JPS63133395A (ja) * 1986-11-25 1988-06-06 Toshiba Corp 半導体記憶装置
JP2590897B2 (ja) * 1987-07-20 1997-03-12 日本電気株式会社 半導体メモリ
JP2509297B2 (ja) * 1987-08-31 1996-06-19 沖電気工業株式会社 自己訂正機能付半導体記憶装置及びマイクロコンピュ―タ
JPH01184787A (ja) * 1988-01-19 1989-07-24 Toshiba Corp 半導体メモリ
US5022006A (en) * 1988-04-01 1991-06-04 International Business Machines Corporation Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells
US5015880A (en) * 1989-10-10 1991-05-14 International Business Machines Corporation CMOS driver circuit
US4999815A (en) * 1990-02-13 1991-03-12 International Business Machines Corporation Low power addressing systems

Also Published As

Publication number Publication date
CA2034027A1 (en) 1991-08-14
MY105290A (en) 1994-09-30
AU6995891A (en) 1991-08-15
JPH0689595A (ja) 1994-03-29
KR920000083A (ko) 1992-01-10
HK62097A (en) 1997-05-16
KR950011728B1 (ko) 1995-10-09
EP0442301B1 (de) 1996-12-04
EP0442301A3 (en) 1993-04-07
JP2539950B2 (ja) 1996-10-02
SG43875A1 (en) 1997-11-14
US5134616A (en) 1992-07-28
CA2034027C (en) 1995-12-19
EP0442301A2 (de) 1991-08-21

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