DE69124470T2 - Initialisierung von Rechnersystemen - Google Patents

Initialisierung von Rechnersystemen

Info

Publication number
DE69124470T2
DE69124470T2 DE69124470T DE69124470T DE69124470T2 DE 69124470 T2 DE69124470 T2 DE 69124470T2 DE 69124470 T DE69124470 T DE 69124470T DE 69124470 T DE69124470 T DE 69124470T DE 69124470 T2 DE69124470 T2 DE 69124470T2
Authority
DE
Germany
Prior art keywords
initialization
computer systems
systems
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69124470T
Other languages
English (en)
Other versions
DE69124470D1 (de
Inventor
Kazuhiko Ikeda
Satoru Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
PFU Ltd
Original Assignee
Fujitsu Ltd
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, PFU Ltd filed Critical Fujitsu Ltd
Publication of DE69124470D1 publication Critical patent/DE69124470D1/de
Application granted granted Critical
Publication of DE69124470T2 publication Critical patent/DE69124470T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
DE69124470T 1990-11-14 1991-11-14 Initialisierung von Rechnersystemen Expired - Fee Related DE69124470T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2306082A JP2760363B2 (ja) 1990-11-14 1990-11-14 初期化処理装置

Publications (2)

Publication Number Publication Date
DE69124470D1 DE69124470D1 (de) 1997-03-13
DE69124470T2 true DE69124470T2 (de) 1997-05-15

Family

ID=17952815

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124470T Expired - Fee Related DE69124470T2 (de) 1990-11-14 1991-11-14 Initialisierung von Rechnersystemen

Country Status (4)

Country Link
US (1) US5418955A (de)
EP (1) EP0486304B1 (de)
JP (1) JP2760363B2 (de)
DE (1) DE69124470T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3461825B2 (ja) * 1991-06-26 2003-10-27 三星電子株式会社 マルチプロセッサ分散型初期化および自己テストシステム
JP3679813B2 (ja) * 1991-07-22 2005-08-03 株式会社日立製作所 並列計算機
JPH0695906A (ja) * 1992-09-17 1994-04-08 Fujitsu Ltd Ｓｃｍｐシステムおけるｓｖｐのｓｓｕ制御権の自動切り替え方法
US5408647A (en) * 1992-10-02 1995-04-18 Compaq Computer Corporation Automatic logical CPU assignment of physical CPUs
US5491788A (en) * 1993-09-10 1996-02-13 Compaq Computer Corp. Method of booting a multiprocessor computer where execution is transferring from a first processor to a second processor based on the first processor having had a critical error
JPH07219913A (ja) * 1994-01-28 1995-08-18 Fujitsu Ltd マルチプロセッサシステムの制御方法及び装置
JP3574170B2 (ja) * 1994-03-17 2004-10-06 富士通株式会社 分散型画像処理装置
GB2290891B (en) * 1994-06-29 1999-02-17 Mitsubishi Electric Corp Multiprocessor system
DE4426001A1 (de) * 1994-07-22 1996-02-01 Sel Alcatel Ag Verfahren zur Überlastvermeidung bei einem Systemanlauf eines Mehrrechnersystems und Mehrrechnersystem dafür
JP3447404B2 (ja) * 1994-12-08 2003-09-16 日本電気株式会社 マルチプロセッサシステム
US5642506A (en) * 1994-12-14 1997-06-24 International Business Machines Corporation Method and apparatus for initializing a multiprocessor system
US5627962A (en) * 1994-12-30 1997-05-06 Compaq Computer Corporation Circuit for reassigning the power-on processor in a multiprocessing system
JP3161319B2 (ja) * 1996-02-14 2001-04-25 日本電気株式会社 マルチプロセッサシステム
JP2830857B2 (ja) * 1996-09-09 1998-12-02 三菱電機株式会社 データストレージシステム及びデータストレージ管理方法
US6298376B1 (en) * 1997-03-07 2001-10-02 General Electric Company Fault tolerant communication monitor for a master/slave system
JP3045400U (ja) * 1997-07-17 1998-01-27 船井電機株式会社 電子機器の仕向地別初期設定装置
US6178445B1 (en) * 1998-03-31 2001-01-23 International Business Machines Corporation System and method for determining which processor is the master processor in a symmetric multi-processor environment
US6701429B1 (en) 1998-12-03 2004-03-02 Telefonaktiebolaget Lm Ericsson(Publ) System and method of start-up in efficient way for multi-processor systems based on returned identification information read from pre-determined memory location
US6550019B1 (en) * 1999-11-04 2003-04-15 International Business Machines Corporation Method and apparatus for problem identification during initial program load in a multiprocessor system
US6639918B1 (en) * 2000-01-18 2003-10-28 Apple Computer, Inc. Method and apparatus for border node behavior on a full-duplex bus
JP4525188B2 (ja) * 2004-06-09 2010-08-18 ソニー株式会社 マルチプロセッサシステム
JP4289293B2 (ja) * 2004-12-20 2009-07-01 日本電気株式会社 起動制御方法、二重化プラットフォームシステム及び情報処理装置
JP5595633B2 (ja) * 2007-02-26 2014-09-24 スパンション エルエルシー シミュレーション方法及びシミュレーション装置
JP5019252B2 (ja) * 2007-03-01 2012-09-05 日本電気株式会社 障害処理方法、プログラム及び情報処理装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358823A (en) * 1977-03-25 1982-11-09 Trw, Inc. Double redundant processor
US4484273A (en) * 1982-09-03 1984-11-20 Sequoia Systems, Inc. Modular computer system
US4596012A (en) * 1983-05-25 1986-06-17 Reed Lockwood W Master controller succession system for bus control access for data-communications local area networks
US4718002A (en) * 1985-06-05 1988-01-05 Tandem Computers Incorporated Method for multiprocessor communications
US4757442A (en) * 1985-06-17 1988-07-12 Nec Corporation Re-synchronization system using common memory bus to transfer restart data from non-faulty processor to failed processor
JPH0821025B2 (ja) * 1986-09-29 1996-03-04 株式会社東芝 マルチプロセッサシステムおよび同システムの初期化方法
JPH0766368B2 (ja) * 1986-10-21 1995-07-19 日新電機株式会社 ブ−トプロセツサ決定方式
JPS63262747A (ja) * 1987-04-20 1988-10-31 Fujitsu Ltd マルチプロセツサシステムにおけるタイマ自動初期設定方式
JPH0769892B2 (ja) * 1987-04-23 1995-07-31 日本電気株式会社 プログラムロ−ド方式
US4951192A (en) * 1987-06-04 1990-08-21 Apollo Computer, Inc. Device for managing software configurations in parallel in a network
US5041966A (en) * 1987-10-06 1991-08-20 Nec Corporation Partially distributed method for clock synchronization
JPH02130666A (ja) * 1988-11-11 1990-05-18 Pfu Ltd マルチプロセッサシステムのシステム再構成方式

Also Published As

Publication number Publication date
EP0486304A2 (de) 1992-05-20
EP0486304B1 (de) 1997-01-29
JP2760363B2 (ja) 1998-05-28
DE69124470D1 (de) 1997-03-13
EP0486304A3 (en) 1993-01-13
US5418955A (en) 1995-05-23
JPH04178871A (ja) 1992-06-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee