DE69125128T2 - Verfahren zum Verbinden eines IC-Chips mit einem mit Leitermuster versehenem Substrat - Google Patents

Verfahren zum Verbinden eines IC-Chips mit einem mit Leitermuster versehenem Substrat

Info

Publication number
DE69125128T2
DE69125128T2 DE69125128T DE69125128T DE69125128T2 DE 69125128 T2 DE69125128 T2 DE 69125128T2 DE 69125128 T DE69125128 T DE 69125128T DE 69125128 T DE69125128 T DE 69125128T DE 69125128 T2 DE69125128 T2 DE 69125128T2
Authority
DE
Germany
Prior art keywords
chip
conductor pattern
substrate provided
substrate
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69125128T
Other languages
English (en)
Other versions
DE69125128D1 (de
Inventor
Koji Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69125128D1 publication Critical patent/DE69125128D1/de
Publication of DE69125128T2 publication Critical patent/DE69125128T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
DE69125128T 1990-12-26 1991-12-27 Verfahren zum Verbinden eines IC-Chips mit einem mit Leitermuster versehenem Substrat Expired - Fee Related DE69125128T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP41428990 1990-12-26

Publications (2)

Publication Number Publication Date
DE69125128D1 DE69125128D1 (de) 1997-04-17
DE69125128T2 true DE69125128T2 (de) 1997-06-19

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DE69125128T Expired - Fee Related DE69125128T2 (de) 1990-12-26 1991-12-27 Verfahren zum Verbinden eines IC-Chips mit einem mit Leitermuster versehenem Substrat

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Country Link
US (1) US5384952A (de)
EP (1) EP0493131B1 (de)
JP (1) JP2940269B2 (de)
DE (1) DE69125128T2 (de)

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US5819406A (en) * 1990-08-29 1998-10-13 Canon Kabushiki Kaisha Method for forming an electrical circuit member
US5318651A (en) * 1991-11-27 1994-06-07 Nec Corporation Method of bonding circuit boards
DE4225138A1 (de) * 1992-07-30 1994-02-03 Daimler Benz Ag Multichipmodul und Verfahren zu dessen Herstellung
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US5384952A (en) 1995-01-31
DE69125128D1 (de) 1997-04-17

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