DE69125339T2 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69125339T2
DE69125339T2 DE69125339T DE69125339T DE69125339T2 DE 69125339 T2 DE69125339 T2 DE 69125339T2 DE 69125339 T DE69125339 T DE 69125339T DE 69125339 T DE69125339 T DE 69125339T DE 69125339 T2 DE69125339 T2 DE 69125339T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69125339T
Other languages
English (en)
Other versions
DE69125339D1 (de
Inventor
Akira Tsujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69125339D1 publication Critical patent/DE69125339D1/de
Publication of DE69125339T2 publication Critical patent/DE69125339T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
DE69125339T 1990-11-09 1991-11-11 Halbleiterspeicheranordnung Expired - Lifetime DE69125339T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2305384A JP2630059B2 (ja) 1990-11-09 1990-11-09 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE69125339D1 DE69125339D1 (de) 1997-04-30
DE69125339T2 true DE69125339T2 (de) 1997-10-23

Family

ID=17944475

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125339T Expired - Lifetime DE69125339T2 (de) 1990-11-09 1991-11-11 Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (1) US5267215A (de)
EP (1) EP0485239B1 (de)
JP (1) JP2630059B2 (de)
KR (1) KR960009946B1 (de)
DE (1) DE69125339T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3358030B2 (ja) * 1993-01-22 2002-12-16 日本テキサス・インスツルメンツ株式会社 半導体メモリ装置及びその初期化方法
JP2600597B2 (ja) * 1993-12-06 1997-04-16 日本電気株式会社 情報伝播用ダイナミック回路
US5424997A (en) * 1994-03-15 1995-06-13 National Semiconductor Corporation Non-volatile semiconductor memory having switching devices for segmentation of a memory page and a method thereof
US5623450A (en) * 1995-09-08 1997-04-22 International Business Machines Corporation Conditional recharge for dynamic logic
US5748554A (en) * 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
US6118726A (en) * 1998-02-02 2000-09-12 International Business Machines Corporation Shared row decoder
US6002275A (en) * 1998-02-02 1999-12-14 International Business Machines Corporation Single ended read write drive for memory
US6246630B1 (en) 1998-02-02 2001-06-12 International Business Machines Corporation Intra-unit column address increment system for memory
US6038634A (en) * 1998-02-02 2000-03-14 International Business Machines Corporation Intra-unit block addressing system for memory
US7500075B1 (en) * 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US8190808B2 (en) 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
KR102022419B1 (ko) 2012-12-28 2019-11-04 에스케이하이닉스 주식회사 가변 저항 메모리 장치 및 그 동작 방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4050061A (en) * 1976-05-03 1977-09-20 Texas Instruments Incorporated Partitioning of MOS random access memory array
US4370575A (en) * 1978-09-22 1983-01-25 Texas Instruments Incorporated High performance dynamic sense amplifier with active loads
JPS589285A (ja) * 1981-07-08 1983-01-19 Toshiba Corp 半導体装置
US4520465A (en) * 1983-05-05 1985-05-28 Motorola, Inc. Method and apparatus for selectively precharging column lines of a memory
JPS632198A (ja) * 1986-06-20 1988-01-07 Mitsubishi Electric Corp ダイナミツク型ｒａｍ
JPS6363197A (ja) * 1986-09-03 1988-03-19 Toshiba Corp 半導体記憶装置
US5172335A (en) * 1987-02-23 1992-12-15 Hitachi, Ltd. Semiconductor memory with divided bit load and data bus lines
JP2618938B2 (ja) * 1987-11-25 1997-06-11 株式会社東芝 半導体記憶装置
EP0333207B1 (de) * 1988-03-18 1997-06-11 Kabushiki Kaisha Toshiba Masken-rom mit Ersatzspeicherzellen
JP2547615B2 (ja) * 1988-06-16 1996-10-23 三菱電機株式会社 読出専用半導体記憶装置および半導体記憶装置
JPH0766666B2 (ja) * 1988-08-29 1995-07-19 三菱電機株式会社 半導体記憶装置
JP2633645B2 (ja) * 1988-09-13 1997-07-23 株式会社東芝 半導体メモリ装置
JPH07105140B2 (ja) * 1988-12-16 1995-11-13 日本電気株式会社 半導体メモリ
US4969125A (en) * 1989-06-23 1990-11-06 International Business Machines Corporation Asynchronous segmented precharge architecture
JPH0713864B2 (ja) * 1989-09-27 1995-02-15 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
JPH04176087A (ja) * 1990-11-07 1992-06-23 Sharp Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR920010632A (ko) 1992-06-26
EP0485239A2 (de) 1992-05-13
JP2630059B2 (ja) 1997-07-16
KR960009946B1 (ko) 1996-07-25
EP0485239A3 (en) 1993-08-11
US5267215A (en) 1993-11-30
EP0485239B1 (de) 1997-03-26
JPH04177692A (ja) 1992-06-24
DE69125339D1 (de) 1997-04-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP