DE69125671T2 - Halbleiter-Speicherbauteil - Google Patents

Halbleiter-Speicherbauteil

Info

Publication number: DE69125671T2
Authority: DE; Germany
Prior art keywords: memory device; semiconductor memory; semiconductor; memory
Prior art date: 1990-09-10
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE69125671T

Other languages

English (en)

Other versions

DE69125671D1 (de

Inventor

Toshiyuki Nishihara

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Sony Corp

Original Assignee

Sony Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1990-09-10

Filing date

1991-09-05

Publication date

1997-11-27

1990-12-26 Priority claimed from JP02414488A external-priority patent/JP3128829B2/ja

1991-09-05 Application filed by Sony Corp filed Critical Sony Corp

1997-05-22 Application granted granted Critical

1997-05-22 Publication of DE69125671D1 publication Critical patent/DE69125671D1/de

1997-11-27 Publication of DE69125671T2 publication Critical patent/DE69125671T2/de

2011-09-06 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

DE69125671T 1990-09-10 1991-09-05 Halbleiter-Speicherbauteil Expired - Fee Related DE69125671T2 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP2239418A JP3003188B2 (ja)	1990-09-10	1990-09-10	半導体メモリ及びその製造方法
JP02414488A JP3128829B2 (ja)	1990-12-26	1990-12-26	半導体メモリ装置

Publications (2)

Publication Number	Publication Date
DE69125671D1 DE69125671D1 (de)	1997-05-22
DE69125671T2 true DE69125671T2 (de)	1997-11-27

Family

ID=26534240

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69125671T Expired - Fee Related DE69125671T2 (de)	1990-09-10	1991-09-05	Halbleiter-Speicherbauteil

Country Status (6)

Country	Link
US (1)	US5424235A (de)
EP (1)	EP0475280B1 (de)
JP (1)	JP3003188B2 (de)
KR (1)	KR100225545B1 (de)
DE (1)	DE69125671T2 (de)
TW (1)	TW200602B (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH0722517A (ja) *	1993-06-22	1995-01-24	Mitsubishi Electric Corp	半導体装置およびその製造方法
US5585284A (en) *	1993-07-02	1996-12-17	Hyundai Electronics Industries Co., Ltd.	Method of manufacturing a SOI DRAM
US5396452A (en) *	1993-07-02	1995-03-07	Wahlstrom; Sven E.	Dynamic random access memory
US6242772B1 (en)	1994-12-12	2001-06-05	Altera Corporation	Multi-sided capacitor in an integrated circuit
KR0140657B1 (ko) *	1994-12-31	1998-06-01	김주용	반도체 소자의 제조방법
US5776789A (en) *	1995-06-05	1998-07-07	Fujitsu Limited	Method for fabricating a semiconductor memory device
US6831322B2 (en)	1995-06-05	2004-12-14	Fujitsu Limited	Semiconductor memory device and method for fabricating the same
JPH0982918A (ja) *	1995-09-19	1997-03-28	Toshiba Corp	半導体記憶装置およびその製造方法
US5882959A (en) *	1996-10-08	1999-03-16	Advanced Micro Devices, Inc.	Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor
US5731217A (en) *	1996-10-08	1998-03-24	Advanced Micro Devices, Inc.	Multi-level transistor fabrication method with a filled upper transistor substrate and interconnection thereto
US5872029A (en) *	1996-11-07	1999-02-16	Advanced Micro Devices, Inc.	Method for forming an ultra high density inverter using a stacked transistor arrangement
US5926700A (en)	1997-05-02	1999-07-20	Advanced Micro Devices, Inc.	Semiconductor fabrication having multi-level transistors and high density interconnect therebetween
US5888872A (en)	1997-06-20	1999-03-30	Advanced Micro Devices, Inc.	Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall
US5818069A (en)	1997-06-20	1998-10-06	Advanced Micro Devices, Inc.	Ultra high density series-connected transistors formed on separate elevational levels
US6423596B1 (en) *	1998-09-29	2002-07-23	Texas Instruments Incorporated	Method for two-sided fabrication of a memory array
US6465331B1 (en) *	2000-08-31	2002-10-15	Micron Technology, Inc.	DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines
DE10105725B4 (de) *	2001-02-08	2008-11-13	Infineon Technologies Ag	Halbleiterchip mit einem Substrat, einer integrierten Schaltung und einer Abschirmvorrichtung
US6800892B2 (en) *	2003-02-10	2004-10-05	Micron Technology, Inc.	Memory devices, and electronic systems comprising memory devices
US6717839B1 (en)	2003-03-31	2004-04-06	Ramtron International Corporation	Bit-line shielding method for ferroelectric memories
KR100615085B1 (ko)	2004-01-12	2006-08-22	삼성전자주식회사	노드 콘택 구조체들, 이를 채택하는 반도체소자들, 이를채택하는 에스램 셀들 및 이를 제조하는 방법들
US7858468B2 (en)	2008-10-30	2010-12-28	Micron Technology, Inc.	Memory devices and formation methods
FR2955200B1 (fr)	2010-01-14	2012-07-20	Soitec Silicon On Insulator	Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree
CN101976681B (zh) *	2010-08-27	2012-09-26	东南大学	一种提高电流密度的p型绝缘体上硅横向器件及其制备工艺
TWI492368B (zh)	2011-01-14	2015-07-11	Semiconductor Energy Lab	半導體記憶裝置
US8686486B2 (en) *	2011-03-31	2014-04-01	Semiconductor Energy Laboratory Co., Ltd.	Memory device
KR102616259B1 (ko) *	2022-05-06	2023-12-20	(주)서연인테크	독립형 푸드 테이블

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3755012A (en) *	1971-03-19	1973-08-28	Motorola Inc	Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor
US4501060A (en) *	1983-01-24	1985-02-26	At&T Bell Laboratories	Dielectrically isolated semiconductor devices
EP0164829B1 (de) *	1984-04-19	1988-09-28	Nippon Telegraph And Telephone Corporation	Halbleiterspeicherbauelement und Verfahren zur Herstellung
US4763180A (en) *	1986-12-22	1988-08-09	International Business Machines Corporation	Method and structure for a high density VMOS dynamic ram array
EP0283964B1 (de) *	1987-03-20	1994-09-28	Nec Corporation	Aus einer Vielzahl von Eintransistorzellen bestehende dynamische Speichervorrichtung mit wahlfreiem Zugriff
JPH0795568B2 (ja) *	1987-04-27	1995-10-11	日本電気株式会社	半導体記憶装置
JP2510865B2 (ja) *	1987-08-20	1996-06-26	日本電信電話株式会社	無線印刷電信における一括呼出方法
JP2590171B2 (ja) *	1988-01-08	1997-03-12	株式会社日立製作所	半導体記憶装置
JPH0235771A (ja) *	1988-07-26	1990-02-06	Nec Corp	半導体記憶装置
JP2743391B2 (ja) *	1988-08-25	1998-04-22	ソニー株式会社	半導体メモリの製造方法
US5192704A (en) *	1989-06-30	1993-03-09	Texas Instruments Incorporated	Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell

1990
- 1990-09-10 JP JP2239418A patent/JP3003188B2/ja not_active Expired - Fee Related
1991
- 1991-09-04 TW TW080107033A patent/TW200602B/zh active
- 1991-09-05 EP EP91115019A patent/EP0475280B1/de not_active Expired - Lifetime
- 1991-09-05 DE DE69125671T patent/DE69125671T2/de not_active Expired - Fee Related
- 1991-09-10 KR KR1019910015732A patent/KR100225545B1/ko not_active IP Right Cessation
1994
- 1994-09-19 US US08/306,434 patent/US5424235A/en not_active Expired - Fee Related

Also Published As

Publication number	Publication date
EP0475280B1 (de)	1997-04-16
KR920007199A (ko)	1992-04-28
US5424235A (en)	1995-06-13
TW200602B (de)	1993-02-21
JPH04118967A (ja)	1992-04-20
JP3003188B2 (ja)	2000-01-24
EP0475280A1 (de)	1992-03-18
KR100225545B1 (ko)	1999-10-15
DE69125671D1 (de)	1997-05-22

Legal Events

Date	Code	Title	Description
1998-05-14	8364	No opposition during term of opposition
2003-07-10	8339	Ceased/non-payment of the annual fee

Publication	Publication Date	Title
DE69132284T2 (de)	2000-11-30	Halbleiterspeicheranordnung
DE69123666T2 (de)	1997-07-10	Halbleiterspeicheranordnung
DE69125671T2 (de)	1997-11-27	Halbleiter-Speicherbauteil
DE69125206T2 (de)	1997-10-09	Halbleiterspeicheranordnung
DE69123379D1 (de)	1997-01-16	Halbleiterspeichervorrichtung
DE69121801T2 (de)	1997-02-13	Halbleiterspeicheranordnung
DE69127155T2 (de)	1998-01-15	Halbleiterspeicheranordnung
DE69125535T2 (de)	1997-07-17	Halbleiterspeicheranordnung
DE69126559T2 (de)	1997-10-02	Halbleiterspeicheranordnung
DE69128061T2 (de)	1998-03-26	Halbleiterspeicheranordnung
DE69125339T2 (de)	1997-10-23	Halbleiterspeicheranordnung
DE69128819T2 (de)	1998-05-14	Halbleiterspeicheranordnung
DE69125734T2 (de)	1997-12-18	Halbleiterspeicheranordnung
DE69123294D1 (de)	1997-01-09	Halbleiterspeicheranordnung
DE69124286T2 (de)	1997-08-14	Halbleiterspeicheranordnung
DE69122293T2 (de)	1997-04-24	Halbleiterspeicheranordnung
DE69125905D1 (de)	1997-06-05	Halbleiterspeicheranordnung
DE69124022D1 (de)	1997-02-20	Halbleiterspeicheranordnung
DE69128400D1 (de)	1998-01-22	Halbleiterspeicheranordnung
DE69121804T2 (de)	1997-02-13	Halbleiterspeicheranordnung
DE69119252T2 (de)	1997-01-02	Halbleiterspeicheranordnung
DE69122909T2 (de)	1997-02-27	Halbleiterspeicheranordnung
DE69119141D1 (de)	1996-06-05	Halbleiterspeicheranordnung
DE69121366D1 (de)	1996-09-19	Halbleiterspeicheranordnung
DE69122192T2 (de)	1997-04-24	Halbleiterspeichereinrichtung