DE69128140D1 - Halbleiteranordnung mit einer Schaltungsplatte zum Zusammenschalten und Verfahren zur Herstellung - Google Patents

Halbleiteranordnung mit einer Schaltungsplatte zum Zusammenschalten und Verfahren zur Herstellung

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Publication number
DE69128140D1
DE69128140D1 DE69128140T DE69128140T DE69128140D1 DE 69128140 D1 DE69128140 D1 DE 69128140D1 DE 69128140 T DE69128140 T DE 69128140T DE 69128140 T DE69128140 T DE 69128140T DE 69128140 D1 DE69128140 D1 DE 69128140D1
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DE
Germany
Prior art keywords
interconnection
manufacturing
circuit board
semiconductor arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69128140T
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English (en)
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DE69128140T2 (de
Inventor
Junya Nagano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69128140D1 publication Critical patent/DE69128140D1/de
Application granted granted Critical
Publication of DE69128140T2 publication Critical patent/DE69128140T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49531Additional leads the additional leads being a wiring board
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
DE69128140T 1990-12-20 1991-12-20 Halbleiteranordnung mit einer Schaltungsplatte zum Zusammenschalten und Verfahren zur Herstellung Expired - Lifetime DE69128140T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP40442990 1990-12-20
JP3326148A JP3011510B2 (ja) 1990-12-20 1991-12-10 相互連結回路基板を有する半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
DE69128140D1 true DE69128140D1 (de) 1997-12-11
DE69128140T2 DE69128140T2 (de) 1998-03-19

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JPH05283601A (ja) 1993-10-29
US5613295A (en) 1997-03-25
US5473514A (en) 1995-12-05
EP0503201A2 (de) 1992-09-16
DE69128140T2 (de) 1998-03-19
US5552966A (en) 1996-09-03
US5646830A (en) 1997-07-08
JP3011510B2 (ja) 2000-02-21
EP0503201B1 (de) 1997-11-05
US5715147A (en) 1998-02-03
EP0503201A3 (de) 1994-03-16

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