DE69132284D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number: DE69132284D1
Authority: DE; Germany
Prior art keywords: memory device; semiconductor memory; semiconductor; memory
Prior art date: 1990-10-15
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE69132284T

Other languages

English (en)

Other versions

DE69132284T2 (de

Inventor

Haruki Toda

Shozo Saito

Kaoru Tokushige

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Toshiba Corp

Original Assignee

Toshiba Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1990-10-15

Filing date

1991-10-15

Publication date

2000-08-10

1991-10-15 Application filed by Toshiba Corp filed Critical Toshiba Corp

2000-08-10 Publication of DE69132284D1 publication Critical patent/DE69132284D1/de

2000-11-30 Application granted granted Critical

2000-11-30 Publication of DE69132284T2 publication Critical patent/DE69132284T2/de

2011-10-16 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

DE69132284T 1990-10-15 1991-10-15 Halbleiterspeicheranordnung Expired - Lifetime DE69132284T2 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP27317090		1990-10-15
JP3255354A JP2740063B2 (ja)	1990-10-15	1991-10-02	半導体記憶装置

Publications (2)

Publication Number	Publication Date
DE69132284D1 true DE69132284D1 (de)	2000-08-10
DE69132284T2 DE69132284T2 (de)	2000-11-30

Family

ID=26542163

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69132284T Expired - Lifetime DE69132284T2 (de)	1990-10-15	1991-10-15	Halbleiterspeicheranordnung

Country Status (4)

Country	Link
US (9)	US5313437A (de)
EP (1)	EP0481437B1 (de)
JP (1)	JP2740063B2 (de)
DE (1)	DE69132284T2 (de)

Families Citing this family (46)

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KR960003526B1 (ko) *	1992-10-02	1996-03-14	삼성전자주식회사	반도체 메모리장치
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JP3406790B2 (ja)	1996-11-25	2003-05-12	株式会社東芝	データ転送システム及びデータ転送方法
US5940608A (en)	1997-02-11	1999-08-17	Micron Technology, Inc.	Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
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FR2761802B1 (fr)	1997-04-08	1999-06-18	Sgs Thomson Microelectronics	Ensemble de deux memoires sur un meme circuit integre monolithique
KR100481828B1 (ko) *	1997-05-19	2005-07-05	삼성전자주식회사	가변어드레스제어장치를이용한메모리제어방법
US6173432B1 (en)	1997-06-20	2001-01-09	Micron Technology, Inc.	Method and apparatus for generating a sequence of clock signals
US5953284A (en)	1997-07-09	1999-09-14	Micron Technology, Inc.	Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
EP2105841A1 (de) *	1997-10-10	2009-09-30	Rambus Inc.	Vorrichtung und Verfahren für Pipeline-Speicherbetrieb mit Schreib-Maskierung
KR100505593B1 (ko) *	1998-02-16	2005-10-14	삼성전자주식회사	동기식 디램 및 이의 데이터 출력 제어방법
US6269451B1 (en)	1998-02-27	2001-07-31	Micron Technology, Inc.	Method and apparatus for adjusting data timing by delaying clock signal
US6590901B1 (en) *	1998-04-01	2003-07-08	Mosaid Technologies, Inc.	Method and apparatus for providing a packet buffer random access memory
US6338127B1 (en)	1998-08-28	2002-01-08	Micron Technology, Inc.	Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en)	1998-09-03	2002-02-19	Micron Technology, Inc.	Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en)	1998-09-03	2001-08-21	Micron Technology, Inc.	Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6430696B1 (en)	1998-11-30	2002-08-06	Micron Technology, Inc.	Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en)	1998-12-11	2002-04-16	Micron Technology, Inc.	Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6469955B1 (en) *	2000-11-21	2002-10-22	Integrated Memory Technologies, Inc.	Integrated circuit memory device having interleaved read and program capabilities and methods of operating same
US6470060B1 (en)	1999-03-01	2002-10-22	Micron Technology, Inc.	Method and apparatus for generating a phase dependent control signal
US6396617B1 (en)	1999-05-17	2002-05-28	Michael Scalora	Photonic band gap device and method using a periodicity defect region doped with a gain medium to increase photonic signal delay
US6859399B1 (en) *	2000-05-17	2005-02-22	Marvell International, Ltd.	Memory architecture and system and multiport interface protocol
US6515914B2 (en)	2001-03-21	2003-02-04	Micron Technology, Inc.	Memory device and method having data path with multiple prefetch I/O configurations
US6801989B2 (en)	2001-06-28	2004-10-05	Micron Technology, Inc.	Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US7168027B2 (en)	2003-06-12	2007-01-23	Micron Technology, Inc.	Dynamic synchronization of data capture on an optical or other high speed communications link
US7624209B1 (en) *	2004-09-15	2009-11-24	Xilinx, Inc.	Method of and circuit for enabling variable latency data transfers
CA2651434A1 (en) *	2006-05-23	2007-11-29	Mosaid Technologies Incorporated	Apparatus and method for establishing device identifiers for serially interconnected devices
JP4708389B2 (ja) *	2007-05-14	2011-06-22	富士通セミコンダクター株式会社	クロック同期型メモリ装置及びそのスケジューラ回路
US9286004B1 (en) *	2014-03-31	2016-03-15	Emc Corporation	Managing I/O operations in multi-core systems
KR20190012571A (ko) *	2017-07-27	2019-02-11	에스케이하이닉스 주식회사	메모리 장치 및 그 동작 방법
JP6476325B1 (ja) *	2018-02-01	2019-02-27	華邦電子股▲ふん▼有限公司ＷｉｎｂｏｎｄＥｌｅｃｔｒｏｎｉｃｓＣｏｒｐ．	擬似ｓｒａｍ及びその制御方法

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KR960003526B1 (ko) *	1992-10-02	1996-03-14	삼성전자주식회사	반도체 메모리장치
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JPS61156338A (ja) *	1984-12-27	1986-07-16	Toshiba Corp	マルチプロセツサシステム
US4648077A (en) *	1985-01-22	1987-03-03	Texas Instruments Incorporated	Video serial accessed memory with midline load
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JPS62223891A (ja) *	1986-03-26	1987-10-01	Hitachi Ltd	半導体記憶装置
JP2587229B2 (ja) *	1987-03-11	1997-03-05	日本テキサス・インスツルメンツ株式会社	アービタ回路
JPH0612609B2 (ja) *	1987-03-27	1994-02-16	株式会社東芝	半導体メモリ
JPS63272191A (ja) *	1987-04-30	1988-11-09	Toshiba Corp	時間軸変動補正回路
JPH01120660A (ja) *	1987-11-04	1989-05-12	Nec Corp	マイクロコンピュータ装置
US5054000A (en) *	1988-02-19	1991-10-01	Sony Corporation	Static random access memory device having a high speed read-out and flash-clear functions
US4922461A (en) *	1988-03-30	1990-05-01	Kabushiki Kaisha Toshiba	Static random access memory with address transition detector
JPH01251496A (ja) *	1988-03-31	1989-10-06	Toshiba Corp	スタティック型ランダムアクセスメモリ
DE68929407T2 (de) *	1988-11-29	2003-01-16	Matsushita Electric Ind Co Ltd	Integrierte Schaltung mit synchronem Halbleiter-Speicher, Methode zum Zugriff auf diesen Speicher und System mit einem solchen Speicher
JPH02279015A (ja) *	1989-04-20	1990-11-15	Sanyo Electric Co Ltd	遅延回路
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JPH03252988A (ja) *	1990-03-02	1991-11-12	Nec Corp	ダイナミック型半導体メモリ
KR100214435B1 (ko) *	1990-07-25	1999-08-02	사와무라 시코	동기식 버스트 엑세스 메모리
JP2740063B2 (ja) *	1990-10-15	1998-04-15	株式会社東芝	半導体記憶装置
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JP3992757B2 (ja) *	1991-04-23	2007-10-17	テキサスインスツルメンツインコーポレイテツド	マイクロプロセッサと同期するメモリ、及びデータプロセッサ、同期メモリ、周辺装置とシステムクロックを含むシステム
US5305277A (en) *	1991-04-24	1994-04-19	International Business Machines Corporation	Data processing apparatus having address decoder supporting wide range of operational frequencies
JPH0574167A (ja) *	1991-09-17	1993-03-26	Nec Corp	半導体記憶装置
JPH0589676A (ja) *	1991-09-25	1993-04-09	Mitsubishi Electric Corp	半導体記憶装置
US5809552A (en) *	1992-01-29	1998-09-15	Fujitsu Limited	Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions
KR950000504B1 (ko) *	1992-01-31	1995-01-24	삼성전자 주식회사	복수개의 로우 어드레스 스트로브 신호를 가지는 반도체 메모리 장치
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1991
- 1991-10-02 JP JP3255354A patent/JP2740063B2/ja not_active Expired - Lifetime
- 1991-10-15 EP EP91117593A patent/EP0481437B1/de not_active Expired - Lifetime
- 1991-10-15 US US07/775,602 patent/US5313437A/en not_active Expired - Lifetime
- 1991-10-15 DE DE69132284T patent/DE69132284T2/de not_active Expired - Lifetime
1994
- 1994-04-05 US US08/223,222 patent/US5500829A/en not_active Expired - Lifetime
1995
- 1995-04-24 US US08/427,270 patent/US5587963A/en not_active Expired - Lifetime
- 1995-06-05 US US08/463,394 patent/US5612925A/en not_active Expired - Lifetime
1996
- 1996-09-27 US US08/720,309 patent/US5737637A/en not_active Expired - Lifetime
1997
- 1997-01-07 US US08/779,902 patent/US5740122A/en not_active Expired - Lifetime
- 1997-08-15 US US08/912,071 patent/US5875486A/en not_active Expired - Lifetime
1998
- 1998-02-03 US US09/017,948 patent/US5926436A/en not_active Expired - Lifetime
1999
- 1999-01-25 US US09/236,832 patent/US5995442A/en not_active Expired - Fee Related

Also Published As

Publication number	Publication date
EP0481437A3 (en)	1993-07-21
US5313437A (en)	1994-05-17
US5737637A (en)	1998-04-07
EP0481437B1 (de)	2000-07-05
JPH052873A (ja)	1993-01-08
US5587963A (en)	1996-12-24
US5500829A (en)	1996-03-19
US5926436A (en)	1999-07-20
JP2740063B2 (ja)	1998-04-15
US5740122A (en)	1998-04-14
US5612925A (en)	1997-03-18
DE69132284T2 (de)	2000-11-30
US5875486A (en)	1999-02-23
US5995442A (en)	1999-11-30
EP0481437A2 (de)	1992-04-22

Legal Events

Date	Code	Title	Description
2001-07-26	8364	No opposition during term of opposition

Publication	Publication Date	Title
DE69132284T2 (de)	2000-11-30	Halbleiterspeicheranordnung
DE69123666T2 (de)	1997-07-10	Halbleiterspeicheranordnung
DE69125671D1 (de)	1997-05-22	Halbleiter-Speicherbauteil
DE69125206D1 (de)	1997-04-24	Halbleiterspeicheranordnung
DE69121801T2 (de)	1997-02-13	Halbleiterspeicheranordnung
DE69123379D1 (de)	1997-01-16	Halbleiterspeichervorrichtung
DE69125535T2 (de)	1997-07-17	Halbleiterspeicheranordnung
DE69127155T2 (de)	1998-01-15	Halbleiterspeicheranordnung
DE69126559T2 (de)	1997-10-02	Halbleiterspeicheranordnung
DE69128061D1 (de)	1997-12-04	Halbleiterspeicheranordnung
DE69125339T2 (de)	1997-10-23	Halbleiterspeicheranordnung
DE69128819D1 (de)	1998-03-05	Halbleiterspeicheranordnung
DE69125734D1 (de)	1997-05-28	Halbleiterspeicheranordnung
DE69123294T2 (de)	1997-05-07	Halbleiterspeicheranordnung
DE69124286D1 (de)	1997-03-06	Halbleiterspeicheranordnung
DE69122293T2 (de)	1997-04-24	Halbleiterspeicheranordnung
DE69125905D1 (de)	1997-06-05	Halbleiterspeicheranordnung
DE69124022T2 (de)	1997-08-14	Halbleiterspeicheranordnung
DE69122909D1 (de)	1996-12-05	Halbleiterspeicheranordnung
DE69121804T2 (de)	1997-02-13	Halbleiterspeicheranordnung
DE69128400D1 (de)	1998-01-22	Halbleiterspeicheranordnung
DE69119141T2 (de)	1996-10-31	Halbleiterspeicheranordnung
DE69119252T2 (de)	1997-01-02	Halbleiterspeicheranordnung
DE69121366T2 (de)	1997-01-23	Halbleiterspeicheranordnung
DE69122192D1 (de)	1996-10-24	Halbleiterspeichereinrichtung