DE69133316D1 - Verfahren zum Herstellen einer Halbleitervorrichtung - Google Patents

Verfahren zum Herstellen einer Halbleitervorrichtung

Info

Publication number
DE69133316D1
DE69133316D1 DE69133316T DE69133316T DE69133316D1 DE 69133316 D1 DE69133316 D1 DE 69133316D1 DE 69133316 T DE69133316 T DE 69133316T DE 69133316 T DE69133316 T DE 69133316T DE 69133316 D1 DE69133316 D1 DE 69133316D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69133316T
Other languages
English (en)
Other versions
DE69133316T2 (de
Inventor
Kyoichi Suguro
Haruo Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69133316D1 publication Critical patent/DE69133316D1/de
Application granted granted Critical
Publication of DE69133316T2 publication Critical patent/DE69133316T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31608Deposition of SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/117Oxidation, selective
DE69133316T 1990-02-14 1991-02-13 Verfahren zum Herstellen einer Halbleitervorrichtung Expired - Fee Related DE69133316T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP3268990 1990-02-14
JP3268990 1990-02-14
JP1658691 1991-02-07
JP01658691A JP3469251B2 (ja) 1990-02-14 1991-02-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69133316D1 true DE69133316D1 (de) 2003-10-30
DE69133316T2 DE69133316T2 (de) 2004-07-22

Family

ID=26352955

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69133316T Expired - Fee Related DE69133316T2 (de) 1990-02-14 1991-02-13 Verfahren zum Herstellen einer Halbleitervorrichtung

Country Status (4)

Country Link
US (4) US5192714A (de)
EP (1) EP0442718B1 (de)
JP (1) JP3469251B2 (de)
DE (1) DE69133316T2 (de)

Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3469251B2 (ja) * 1990-02-14 2003-11-25 株式会社東芝 半導体装置の製造方法
JPH05102136A (ja) * 1991-10-03 1993-04-23 Toshiba Corp 半導体集積回路装置の製造方法
KR950012918B1 (ko) * 1991-10-21 1995-10-23 현대전자산업주식회사 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법
EP0603461A3 (de) * 1992-10-30 1996-09-25 Ibm Herstellung von 3-D Siliziumsilizid-Strukturen.
US5436173A (en) * 1993-01-04 1995-07-25 Texas Instruments Incorporated Method for forming a semiconductor on insulator device
US5719447A (en) * 1993-06-03 1998-02-17 Intel Corporation Metal alloy interconnections for integrated circuits
JP3404873B2 (ja) * 1994-03-25 2003-05-12 株式会社デンソー 半導体装置の製造方法
EP0690494B1 (de) * 1994-06-27 2004-03-17 Infineon Technologies AG Verbindungs- und Aufbautechnik für Multichip-Module
KR0134108B1 (ko) * 1994-06-30 1998-04-20 김주용 반도체 소자의 제조방법
JPH0851103A (ja) * 1994-08-08 1996-02-20 Fuji Electric Co Ltd 薄膜の生成方法
JPH08148563A (ja) * 1994-11-22 1996-06-07 Nec Corp 半導体装置の多層配線構造体の形成方法
KR0138307B1 (ko) * 1994-12-14 1998-06-01 김광호 반도체 장치의 측면콘택 형성방법
JP3176017B2 (ja) * 1995-02-15 2001-06-11 株式会社東芝 半導体装置の製造方法
JP3073906B2 (ja) * 1995-03-27 2000-08-07 財団法人国際超電導産業技術研究センター 超電導デバイスの製造方法
US5626786A (en) * 1995-04-17 1997-05-06 Huntington; John H. Labile bromine fire suppressants
US5547900A (en) * 1995-05-26 1996-08-20 United Microelectronics Corporation Method of fabricating a self-aligned contact using a liquid-phase oxide-deposition process
JPH0922896A (ja) * 1995-07-07 1997-01-21 Toshiba Corp 金属膜の選択的形成方法
US5504030A (en) * 1995-07-21 1996-04-02 United Microelectronics Corporation Process for fabricating high-density mask ROM devices
US5856707A (en) * 1995-09-11 1999-01-05 Stmicroelectronics, Inc. Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in which they are formed
US6069370A (en) * 1997-03-26 2000-05-30 Nec Corporation Field-effect transistor and fabrication method thereof and image display apparatus
JPH09153616A (ja) * 1995-09-28 1997-06-10 Toshiba Corp 半導体装置およびその製造方法
JP2830812B2 (ja) * 1995-12-27 1998-12-02 日本電気株式会社 多層プリント配線板の製造方法
US5972788A (en) 1996-05-22 1999-10-26 International Business Machines Corporation Method of making flexible interconnections with dual-metal-dual-stud structure
US5846876A (en) * 1996-06-05 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit which uses a damascene process for producing staggered interconnect lines
US6077768A (en) * 1996-07-19 2000-06-20 Motorola, Inc. Process for fabricating a multilevel interconnect
US6001420A (en) 1996-09-23 1999-12-14 Applied Materials, Inc. Semi-selective chemical vapor deposition
US6066548A (en) 1996-10-31 2000-05-23 Micron Technology, Inc. Advance metallization process
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
US6121159A (en) 1997-06-19 2000-09-19 Lsi Logic Corporation Polymeric dielectric layers having low dielectric constants and improved adhesion to metal lines
US5969805A (en) 1997-11-04 1999-10-19 Micron Technology, Inc. Method and apparatus employing external light source for endpoint detection
US6704107B1 (en) 1997-11-04 2004-03-09 Micron Technology, Inc. Method and apparatus for automated, in situ material detection using filtered fluoresced, reflected, or absorbed light
US7102737B2 (en) * 1997-11-04 2006-09-05 Micron Technology, Inc. Method and apparatus for automated, in situ material detection using filtered fluoresced, reflected, or absorbed light
JP3523093B2 (ja) * 1997-11-28 2004-04-26 株式会社東芝 半導体装置およびその製造方法
US6140235A (en) * 1997-12-05 2000-10-31 Applied Materials, Inc. High pressure copper fill at low temperature
JP3123512B2 (ja) * 1998-06-02 2001-01-15 日本電気株式会社 半導体装置及びその製造方法
JP3431128B2 (ja) * 1998-08-05 2003-07-28 シャープ株式会社 半導体装置の製造方法
US6207493B1 (en) * 1998-08-19 2001-03-27 International Business Machines Corporation Formation of out-diffused bitline by laser anneal
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
JP2000195814A (ja) * 1998-12-28 2000-07-14 Fujitsu Ltd 半導体装置の製造方法
KR100313510B1 (ko) * 1999-04-02 2001-11-07 김영환 반도체 소자의 제조방법
EP1050905B1 (de) * 1999-05-07 2017-06-21 Shinko Electric Industries Co. Ltd. Verfahren zur Herstellung einer Halbleitervorrichtung mit isolierender Schicht
US6521501B1 (en) * 1999-05-11 2003-02-18 Advanced Micro Devices, Inc. Method of forming a CMOS transistor having ultra shallow source and drain regions
KR100498855B1 (ko) * 1999-07-01 2005-07-04 인피네온 테크놀로지스 아게 집적 반도체 구조물 내에 규화된 폴리실리콘 콘택을제조하기 위한 방법
US6395631B1 (en) * 1999-08-04 2002-05-28 Chartered Semiconductor Manufacturing Ltd. Low dielectric constant dielectric layer fabrication method employing hard mask layer delamination
US6869750B2 (en) * 1999-10-28 2005-03-22 Fujitsu Limited Structure and method for forming a multilayered structure
US6882045B2 (en) * 1999-10-28 2005-04-19 Thomas J. Massingill Multi-chip module and method for forming and method for deplating defective capacitors
US6428942B1 (en) * 1999-10-28 2002-08-06 Fujitsu Limited Multilayer circuit structure build up method
KR101050377B1 (ko) * 2001-02-12 2011-07-20 에이에스엠 아메리카, 인코포레이티드 반도체 박막 증착을 위한 개선된 공정
JP2003023070A (ja) * 2001-07-05 2003-01-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6383930B1 (en) * 2001-07-12 2002-05-07 Taiwan Semiconductor Manufacturing Company Method to eliminate copper CMP residue of an alignment mark for damascene processes
KR100440472B1 (ko) * 2001-12-13 2004-07-14 아남반도체 주식회사 반도체 소자 제조 방법
JP2003224279A (ja) * 2002-01-31 2003-08-08 Oki Electric Ind Co Ltd 電界効果トランジスタ素子
US6797620B2 (en) * 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture
US6593221B1 (en) 2002-08-13 2003-07-15 Micron Technology, Inc. Selective passivation of exposed silicon
US7186630B2 (en) * 2002-08-14 2007-03-06 Asm America, Inc. Deposition of amorphous silicon-containing films
US7138690B2 (en) * 2003-07-21 2006-11-21 Agere Systems Inc. Shielding structure for use in a metal-oxide-semiconductor device
JP4581119B2 (ja) * 2003-09-17 2010-11-17 株式会社トリケミカル研究所 NiSi膜形成材料およびNiSi膜形成方法
JP2005217176A (ja) * 2004-01-29 2005-08-11 Tokyo Electron Ltd 半導体装置および積層膜の形成方法
US7280068B2 (en) * 2005-07-14 2007-10-09 Agilent Technologies, Inc. System and method for microwave imaging with suppressed sidelobes using a sparse antenna array
US7473999B2 (en) * 2005-09-23 2009-01-06 Megica Corporation Semiconductor chip and process for forming the same
US20070087573A1 (en) * 2005-10-19 2007-04-19 Yi-Yiing Chiang Pre-treatment method for physical vapor deposition of metal layer and method of forming metal silicide layer
JP4703364B2 (ja) * 2005-10-24 2011-06-15 株式会社東芝 半導体装置及びその製造方法
US7382658B2 (en) * 2006-01-26 2008-06-03 Mosys, Inc. Non-volatile memory embedded in a conventional logic process and methods for operating same
US20070170489A1 (en) * 2006-01-26 2007-07-26 Fang Gang-Feng Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process
JP5110885B2 (ja) * 2007-01-19 2012-12-26 キヤノン株式会社 複数の導電性の領域を有する構造体
KR100857229B1 (ko) * 2007-05-28 2008-09-05 삼성전자주식회사 반도체 소자 및 그 형성방법
US8551877B2 (en) * 2012-03-07 2013-10-08 Tokyo Electron Limited Sidewall and chamfer protection during hard mask removal for interconnect patterning
US10453749B2 (en) * 2017-02-14 2019-10-22 Tokyo Electron Limited Method of forming a self-aligned contact using selective SiO2 deposition
US10256405B2 (en) 2017-04-05 2019-04-09 International Business Machines Corporation Methods for fabricating artificial neural networks (ANN) based on doped semiconductor elements
US10586734B2 (en) * 2017-11-20 2020-03-10 Tokyo Electron Limited Method of selective film deposition for forming fully self-aligned vias
CN111128708A (zh) * 2019-12-18 2020-05-08 华虹半导体(无锡)有限公司 自对准金属硅化物及晶体管中接触层的形成方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL191683C (nl) * 1977-02-21 1996-02-05 Zaidan Hojin Handotai Kenkyu Halfgeleidergeheugenschakeling.
JPS56105652A (en) * 1980-01-28 1981-08-22 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS56135944A (en) * 1980-03-28 1981-10-23 Fujitsu Ltd Manufacture of semiconductor device
JPS57126131A (en) * 1981-01-28 1982-08-05 Toshiba Corp Manufacture of semiconductor device
US4493740A (en) * 1981-06-01 1985-01-15 Matsushita Electric Industrial Company, Limited Method for formation of isolation oxide regions in semiconductor substrates
JPS584947A (ja) * 1981-06-30 1983-01-12 Nippon Telegr & Teleph Corp <Ntt> 埋込配線層の形成法
CA1200624A (en) * 1981-08-10 1986-02-11 Susumu Muramoto Method for the manufacture of semiconductor device using refractory metal in a lift-off step
JPS59144151A (ja) * 1983-02-08 1984-08-18 Nec Corp 半導体装置の製造方法
JPS61111562A (ja) * 1984-11-05 1986-05-29 Mitsubishi Electric Corp 半導体装置の製造方法
JPS61137344A (ja) * 1984-12-07 1986-06-25 Toshiba Corp 半導体装置の製造方法
US5084414A (en) * 1985-03-15 1992-01-28 Hewlett-Packard Company Metal interconnection system with a planar surface
DE3650077T2 (de) * 1985-03-15 1995-02-23 Hewlett Packard Co Metallisches Verbindungssystem mit einer ebenen Fläche.
KR880000483B1 (ko) * 1985-08-05 1988-04-07 재단법인 한국전자통신 연구소 반도체소자의 제조방법
JPH0779133B2 (ja) * 1986-06-12 1995-08-23 松下電器産業株式会社 半導体装置の製造方法
US5069749A (en) * 1986-07-29 1991-12-03 Digital Equipment Corporation Method of fabricating interconnect layers on an integrated circuit chip using seed-grown conductors
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US4746621A (en) * 1986-12-05 1988-05-24 Cornell Research Foundation, Inc. Planar tungsten interconnect
US4948755A (en) * 1987-10-08 1990-08-14 Standard Microsystems Corporation Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
US5104694A (en) * 1989-04-21 1992-04-14 Nippon Telephone & Telegraph Corporation Selective chemical vapor deposition of a metallic film on the silicon surface
JPH02307221A (ja) * 1989-05-22 1990-12-20 Nec Corp Cvd膜の成長方法
US4923826A (en) * 1989-08-02 1990-05-08 Harris Corporation Method for forming dielectrically isolated transistor
US5017317A (en) * 1989-12-04 1991-05-21 Board Of Regents, The Uni. Of Texas System Gas phase selective beam deposition
JP3469251B2 (ja) * 1990-02-14 2003-11-25 株式会社東芝 半導体装置の製造方法
US5068207A (en) * 1990-04-30 1991-11-26 At&T Bell Laboratories Method for producing a planar surface in integrated circuit manufacturing
US5120572A (en) * 1990-10-30 1992-06-09 Microelectronics And Computer Technology Corporation Method of fabricating electrical components in high density substrates
JP2773530B2 (ja) * 1992-04-15 1998-07-09 日本電気株式会社 半導体装置の製造方法
US5290358A (en) * 1992-09-30 1994-03-01 International Business Machines Corporation Apparatus for directional low pressure chemical vapor deposition (DLPCVD)
US5518959A (en) * 1995-08-24 1996-05-21 Taiwan Semiconductor Manufacturing Company Method for selectively depositing silicon oxide spacer layers
JP3809545B2 (ja) * 1997-09-19 2006-08-16 株式会社日立製作所 冷蔵庫

Also Published As

Publication number Publication date
EP0442718A3 (en) 1993-08-11
JP3469251B2 (ja) 2003-11-25
EP0442718A2 (de) 1991-08-21
JPH04211121A (ja) 1992-08-03
US5304510A (en) 1994-04-19
EP0442718B1 (de) 2003-09-24
DE69133316T2 (de) 2004-07-22
US5654237A (en) 1997-08-05
US5192714A (en) 1993-03-09
US5470791A (en) 1995-11-28

Similar Documents

Publication Publication Date Title
DE69133316D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69030229D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69033736T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69022087T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE69031543D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE68917995D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE69031184D1 (de) Verfahren zum Herstellen einer Halbleiterbauelement-Packung
DE68919549T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE68911621T2 (de) Verfahren zum Herstellen einer Einrichtung.
DE69028964T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE68920094T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE68926656D1 (de) Verfahren zum Herstellen eines Halbleiterbauelementes
DE68906034T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE69120975D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69506646T2 (de) Verfahren zum Herstellen einer Halbleitereinrichtung
DE69022710D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE3883856T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE68922085D1 (de) Halbleiteranordung und Verfahren zum Herstellen einer Halbleiteranordung.
DE3888457D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE69018884T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE69116592T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE69229288T2 (de) Verfahren zum Herstellen einer Halbleiterspeicheranordnung
DE69116938D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE69128326T2 (de) Ein Verfahren zum Herstellen einer Halbleiteranordnung
DE69429636T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee