DE69215709T2 - Programmierbarer Zwischenschaltungsaufbau mit gemischtem analog/digitalem Betrieb - Google Patents

Programmierbarer Zwischenschaltungsaufbau mit gemischtem analog/digitalem Betrieb

Info

Publication number
DE69215709T2
DE69215709T2 DE69215709T DE69215709T DE69215709T2 DE 69215709 T2 DE69215709 T2 DE 69215709T2 DE 69215709 T DE69215709 T DE 69215709T DE 69215709 T DE69215709 T DE 69215709T DE 69215709 T2 DE69215709 T2 DE 69215709T2
Authority
DE
Germany
Prior art keywords
analog
digital
configurable
circuit structure
user
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69215709T
Other languages
English (en)
Other versions
DE69215709D1 (de
Inventor
Ayat Khaled A El
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi SoC Corp
Original Assignee
Actel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Actel Corp filed Critical Actel Corp
Publication of DE69215709D1 publication Critical patent/DE69215709D1/de
Application granted granted Critical
Publication of DE69215709T2 publication Critical patent/DE69215709T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
DE69215709T 1991-02-13 1992-01-29 Programmierbarer Zwischenschaltungsaufbau mit gemischtem analog/digitalem Betrieb Expired - Fee Related DE69215709T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/654,966 US5107146A (en) 1991-02-13 1991-02-13 Mixed mode analog/digital programmable interconnect architecture

Publications (2)

Publication Number Publication Date
DE69215709D1 DE69215709D1 (de) 1997-01-23
DE69215709T2 true DE69215709T2 (de) 1997-06-19

Family

ID=24626945

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69215709T Expired - Fee Related DE69215709T2 (de) 1991-02-13 1992-01-29 Programmierbarer Zwischenschaltungsaufbau mit gemischtem analog/digitalem Betrieb

Country Status (5)

Country Link
US (1) US5107146A (de)
EP (1) EP0499383B1 (de)
JP (1) JPH05267458A (de)
AT (1) ATE146316T1 (de)
DE (1) DE69215709T2 (de)

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Also Published As

Publication number Publication date
DE69215709D1 (de) 1997-01-23
EP0499383B1 (de) 1996-12-11
EP0499383A2 (de) 1992-08-19
JPH05267458A (ja) 1993-10-15
US5107146A (en) 1992-04-21
ATE146316T1 (de) 1996-12-15
EP0499383A3 (en) 1993-10-27

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