DE69217761T2 - Lese- und Schreibschaltung für einen Speicher - Google Patents

Lese- und Schreibschaltung für einen Speicher

Info

Publication number
DE69217761T2
DE69217761T2 DE69217761T DE69217761T DE69217761T2 DE 69217761 T2 DE69217761 T2 DE 69217761T2 DE 69217761 T DE69217761 T DE 69217761T DE 69217761 T DE69217761 T DE 69217761T DE 69217761 T2 DE69217761 T2 DE 69217761T2
Authority
DE
Germany
Prior art keywords
read
memory
write circuit
write
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69217761T
Other languages
English (en)
Other versions
DE69217761D1 (de
Inventor
Trevor Kenneth Monk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd filed Critical SGS Thomson Microelectronics Ltd
Application granted granted Critical
Publication of DE69217761D1 publication Critical patent/DE69217761D1/de
Publication of DE69217761T2 publication Critical patent/DE69217761T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
DE69217761T 1991-07-30 1992-07-14 Lese- und Schreibschaltung für einen Speicher Expired - Fee Related DE69217761T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB919116493A GB9116493D0 (en) 1991-07-30 1991-07-30 Read and write circuitry for a memory

Publications (2)

Publication Number Publication Date
DE69217761D1 DE69217761D1 (de) 1997-04-10
DE69217761T2 true DE69217761T2 (de) 1997-07-31

Family

ID=10699264

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69217761T Expired - Fee Related DE69217761T2 (de) 1991-07-30 1992-07-14 Lese- und Schreibschaltung für einen Speicher

Country Status (5)

Country Link
US (1) US5321651A (de)
EP (1) EP0526029B1 (de)
JP (1) JPH05210567A (de)
DE (1) DE69217761T2 (de)
GB (1) GB9116493D0 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5513143A (en) * 1992-07-31 1996-04-30 Sgs-Thomson Microelectronics, Inc. Data cache memory internal circuitry for reducing wait states
JPH0728695A (ja) * 1993-07-08 1995-01-31 Nec Corp メモリコントローラ
US5511025A (en) * 1993-10-18 1996-04-23 Texas Instruments Incorporated Write per bit with write mask information carried on the data path past the input data latch
KR960008824B1 (en) * 1993-11-17 1996-07-05 Samsung Electronics Co Ltd Multi bit test circuit and method of semiconductor memory device
EP0655713B1 (de) * 1993-11-26 2000-08-23 Kabushiki Kaisha Toshiba Computertomograph
KR0139776B1 (ko) * 1993-11-26 1998-07-15 이헌조 씨디 그래픽스 디코더의 디램제어장치
JP3304577B2 (ja) * 1993-12-24 2002-07-22 三菱電機株式会社 半導体記憶装置とその動作方法
US5717625A (en) * 1993-12-27 1998-02-10 Kabushiki Kaisha Toshiba Semiconductor memory device
US5926828A (en) * 1996-02-09 1999-07-20 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US6243768B1 (en) 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
JP2888201B2 (ja) * 1996-07-30 1999-05-10 日本電気株式会社 半導体メモリ集積回路
US6201739B1 (en) * 1996-09-20 2001-03-13 Intel Corporation Nonvolatile writeable memory with preemption pin
US5949696A (en) * 1997-06-30 1999-09-07 Cypress Semiconductor Corporation Differential dynamic content addressable memory and high speed network address filtering
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6125065A (en) * 1998-09-09 2000-09-26 Fujitsu Limited Semiconductor memory with column gates and method of controlling column gates during a write mask operation
JP2000235800A (ja) 1999-02-12 2000-08-29 Mitsubishi Electric Corp 半導体記憶装置
US6141249A (en) * 1999-04-01 2000-10-31 Lexar Media, Inc. Organization of blocks within a nonvolatile memory unit to effectively decrease sector write operation time
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
JP2001142869A (ja) * 1999-11-17 2001-05-25 Matsushita Electric Ind Co Ltd システム集積回路
JP4090165B2 (ja) * 1999-11-22 2008-05-28 富士通株式会社 半導体記憶装置
US7299314B2 (en) * 2003-12-31 2007-11-20 Sandisk Corporation Flash storage system with write/erase abort detection mechanism
US7505295B1 (en) * 2004-07-01 2009-03-17 Netlogic Microsystems, Inc. Content addressable memory with multi-row write function
JP4749689B2 (ja) * 2004-08-31 2011-08-17 三洋電機株式会社 メモリ制御回路及びメモリ制御方法
US7783845B2 (en) * 2005-11-14 2010-08-24 Sandisk Corporation Structures for the management of erase operations in non-volatile memories
US7624239B2 (en) * 2005-11-14 2009-11-24 Sandisk Corporation Methods for the management of erase operations in non-volatile memories
JP2007305027A (ja) * 2006-05-15 2007-11-22 Toshiba Corp 汎用レジスタ回路
US8239637B2 (en) * 2007-01-19 2012-08-07 Spansion Llc Byte mask command for memories
US20080320253A1 (en) * 2007-06-19 2008-12-25 Andrew Tomlin Memory device with circuitry for writing data of an atomic transaction
US8266391B2 (en) * 2007-06-19 2012-09-11 SanDisk Technologies, Inc. Method for writing data of an atomic transaction to a memory device
US8775758B2 (en) * 2007-12-28 2014-07-08 Sandisk Technologies Inc. Memory device and method for performing a write-abort-safe firmware update
US9135984B2 (en) * 2013-12-18 2015-09-15 Micron Technology, Inc. Apparatuses and methods for writing masked data to a buffer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4670858A (en) * 1983-06-07 1987-06-02 Tektronix, Inc. High storage capacity associative memory
US4882709A (en) * 1988-08-25 1989-11-21 Integrated Device Technology, Inc. Conditional write RAM
DE69020384T2 (de) * 1989-02-27 1996-03-21 Nec Corp Integrierte Halbleiterspeicherschaltung mit Möglichkeit zum Maskieren des Schreibens im Speicher.
US5239642A (en) * 1991-04-02 1993-08-24 Motorola, Inc. Data processor with shared control and drive circuitry for both breakpoint and content addressable storage devices

Also Published As

Publication number Publication date
GB9116493D0 (en) 1991-09-11
US5321651A (en) 1994-06-14
EP0526029B1 (de) 1997-03-05
JPH05210567A (ja) 1993-08-20
DE69217761D1 (de) 1997-04-10
EP0526029A1 (de) 1993-02-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee