DE69219165T2 - Prüf- und Einbrennsystem für einen Wafer und Methode für deren Herstellung - Google Patents

Prüf- und Einbrennsystem für einen Wafer und Methode für deren Herstellung

Info

Publication number
DE69219165T2
DE69219165T2 DE69219165T DE69219165T DE69219165T2 DE 69219165 T2 DE69219165 T2 DE 69219165T2 DE 69219165 T DE69219165 T DE 69219165T DE 69219165 T DE69219165 T DE 69219165T DE 69219165 T2 DE69219165 T2 DE 69219165T2
Authority
DE
Germany
Prior art keywords
wafer
testing
manufacture
baking system
baking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69219165T
Other languages
English (en)
Other versions
DE69219165D1 (de
Inventor
Anthony M Chiu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69219165D1 publication Critical patent/DE69219165D1/de
Application granted granted Critical
Publication of DE69219165T2 publication Critical patent/DE69219165T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
DE69219165T 1991-01-11 1992-01-09 Prüf- und Einbrennsystem für einen Wafer und Methode für deren Herstellung Expired - Fee Related DE69219165T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US64019891A 1991-01-11 1991-01-11

Publications (2)

Publication Number Publication Date
DE69219165D1 DE69219165D1 (de) 1997-05-28
DE69219165T2 true DE69219165T2 (de) 1997-08-07

Family

ID=24567262

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69219165T Expired - Fee Related DE69219165T2 (de) 1991-01-11 1992-01-09 Prüf- und Einbrennsystem für einen Wafer und Methode für deren Herstellung

Country Status (5)

Country Link
US (3) US5307010A (de)
EP (1) EP0494782B1 (de)
KR (1) KR100274558B1 (de)
DE (1) DE69219165T2 (de)
TW (1) TW207587B (de)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829128A (en) 1993-11-16 1998-11-03 Formfactor, Inc. Method of mounting resilient contact structures to semiconductor devices
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US7511520B2 (en) * 1990-08-29 2009-03-31 Micron Technology, Inc. Universal wafer carrier for wafer level die burn-in
US5905382A (en) 1990-08-29 1999-05-18 Micron Technology, Inc. Universal wafer carrier for wafer level die burn-in
KR100288344B1 (ko) * 1991-09-17 2001-11-30 마쯔모또 에이찌 프린트배선판용검사전극유니트와그것을포함하는검사장치및프린트배선판용의검사방법
US5424651A (en) * 1992-03-27 1995-06-13 Green; Robert S. Fixture for burn-in testing of semiconductor wafers, and a semiconductor wafer
US5457400A (en) * 1992-04-10 1995-10-10 Micron Technology, Inc. Semiconductor array having built-in test circuit for wafer level testing
JPH06230086A (ja) * 1992-09-22 1994-08-19 Nec Corp Ｌｓｉのテスト回路
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
US5399505A (en) * 1993-07-23 1995-03-21 Motorola, Inc. Method and apparatus for performing wafer level testing of integrated circuit dice
US5594273A (en) * 1993-07-23 1997-01-14 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where test pads lie within integrated circuit die but overly no active circuitry for improved yield
US20020053734A1 (en) 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
DE4400118A1 (de) * 1994-01-04 1995-07-06 Siemens Ag Verfahren zum Durchführen von Burn-in-Prozeduren an Halbleiterchips
US5831918A (en) 1994-02-14 1998-11-03 Micron Technology, Inc. Circuit and method for varying a period of an internal control signal during a test mode
US6587978B1 (en) 1994-02-14 2003-07-01 Micron Technology, Inc. Circuit and method for varying a pulse width of an internal control signal during a test mode
US5532174A (en) * 1994-04-22 1996-07-02 Lsi Logic Corporation Wafer level integrated circuit testing with a sacrificial metal layer
US5698895A (en) * 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US5554940A (en) * 1994-07-05 1996-09-10 Motorola, Inc. Bumped semiconductor device and method for probing the same
US5448179A (en) * 1994-07-12 1995-09-05 The United States Of America As Represented By The Secretary Of The Air Force Screening of conductors and contacts on microelectronic devices
US6577148B1 (en) 1994-08-31 2003-06-10 Motorola, Inc. Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer
US5517127A (en) * 1995-01-09 1996-05-14 International Business Machines Corporation Additive structure and method for testing semiconductor wire bond dies
US5952838A (en) * 1995-06-21 1999-09-14 Sony Corporation Reconfigurable array of test structures and method for testing an array of test structures
US5600257A (en) * 1995-08-09 1997-02-04 International Business Machines Corporation Semiconductor wafer test and burn-in
GB2307783B (en) * 1995-09-30 2000-04-05 Motorola Ltd Enhanced security semiconductor device, semiconductor circuit arrangement, and method of production thereof
US5937270A (en) * 1996-01-24 1999-08-10 Micron Electronics, Inc. Method of efficiently laser marking singulated semiconductor devices
JPH09330934A (ja) * 1996-06-12 1997-12-22 Toshiba Corp 半導体装置及びその製造方法
US5852581A (en) * 1996-06-13 1998-12-22 Micron Technology, Inc. Method of stress testing memory integrated circuits
US5991214A (en) * 1996-06-14 1999-11-23 Micron Technology, Inc. Circuit and method for varying a period of an internal control signal during a test mode
WO1998007192A1 (en) * 1996-08-12 1998-02-19 Intercell Corporation Memory module assembly using partially defective chips
US6119049A (en) * 1996-08-12 2000-09-12 Tandon Associates, Inc. Memory module assembly using partially defective chips
JPH10135756A (ja) * 1996-10-31 1998-05-22 Mitsumi Electric Co Ltd 回路体における回路特性の調整方法
US5859442A (en) * 1996-12-03 1999-01-12 Micron Technology, Inc. Circuit and method for configuring a redundant bond pad for probing a semiconductor
JP2001507520A (ja) * 1997-05-23 2001-06-05 アルパイン・マイクロシステムズ・インコーポレイテッド 集積回路パッケージングのための構造体及び方法
US6175161B1 (en) 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6233185B1 (en) 1997-08-21 2001-05-15 Micron Technology, Inc. Wafer level burn-in of memory integrated circuits
RU2133522C1 (ru) * 1997-11-03 1999-07-20 Закрытое акционерное общество "Техно-ТМ" Способ изготовления и контроля электронных компонентов
US5952843A (en) * 1998-03-24 1999-09-14 Vinh; Nguyen T. Variable contact pressure probe
US6303988B1 (en) 1998-04-22 2001-10-16 Packard Hughes Interconnect Company Wafer scale burn-in socket
WO2000026681A1 (de) * 1998-11-02 2000-05-11 Atg Test Systems Gmbh & Co. Kg Vorrichtung zum prüfen von leiterplatten
US6233184B1 (en) 1998-11-13 2001-05-15 International Business Machines Corporation Structures for wafer level test and burn-in
US6262388B1 (en) 1998-12-21 2001-07-17 Micron Electronics, Inc. Laser marking station with enclosure and method of operation
US6417484B1 (en) 1998-12-21 2002-07-09 Micron Electronics, Inc. Laser marking system for dice carried in trays and method of operation
US6348742B1 (en) * 1999-01-25 2002-02-19 Clear Logic, Inc. Sacrificial bond pads for laser configured integrated circuits
US6214180B1 (en) 1999-02-25 2001-04-10 International Business Machines Corporation Method for shorting pin grid array pins for plating
US6261852B1 (en) * 1999-04-19 2001-07-17 Taiwan Semiconductor Manufacturing Company Check abnormal contact and via holes by electroplating method
US6337576B1 (en) 1999-07-19 2002-01-08 Alpine Microsystems, Inc. Wafer-level burn-in
DE19936321C2 (de) * 1999-08-02 2003-12-24 Infineon Technologies Ag Anordnung und Verfahren zum Testen einer Vielzahl von Halbleiterchips auf Waferebene
JP2001135597A (ja) * 1999-08-26 2001-05-18 Fujitsu Ltd 半導体装置の製造方法
US7132841B1 (en) * 2000-06-06 2006-11-07 International Business Machines Corporation Carrier for test, burn-in, and first level packaging
US6603323B1 (en) * 2000-07-10 2003-08-05 Formfactor, Inc. Closed-grid bus architecture for wafer interconnect structure
US6528760B1 (en) 2000-07-14 2003-03-04 Micron Technology, Inc. Apparatus and method using rotational indexing for laser marking IC packages carried in trays
US6524881B1 (en) * 2000-08-25 2003-02-25 Micron Technology, Inc. Method and apparatus for marking a bare semiconductor die
JP2002303653A (ja) * 2001-01-30 2002-10-18 Hitachi Ltd 半導体集積回路装置
JP4248761B2 (ja) * 2001-04-27 2009-04-02 新光電気工業株式会社 半導体パッケージ及びその製造方法並びに半導体装置
US6861859B1 (en) * 2001-10-22 2005-03-01 Electroglas, Inc. Testing circuits on substrates
DE10152086B4 (de) * 2001-10-23 2007-03-22 Infineon Technologies Ag Verfahren zum Testen einer Mehrzahl von Bauelementen auf einem Wafer mit einer gemeinsamen Datenleitung und einer gemeinsamen Versorgungsleitung
US6844218B2 (en) * 2001-12-27 2005-01-18 Texas Instruments Incorporated Semiconductor wafer with grouped integrated circuit die having inter-die connections for group testing
US6756244B2 (en) * 2002-01-29 2004-06-29 Hewlett-Packard Development Company, L.P. Interconnect structure
US7169685B2 (en) 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US7579681B2 (en) * 2002-06-11 2009-08-25 Micron Technology, Inc. Super high density module with integrated wafer level packages
KR100496862B1 (ko) * 2002-10-01 2005-06-22 삼성전자주식회사 멀티칩패키지의 테스트 장치 및 방법
US7180318B1 (en) * 2004-10-15 2007-02-20 Xilinx, Inc. Multi-pitch test probe assembly for testing semiconductor dies having contact pads
US20070111340A1 (en) * 2005-11-15 2007-05-17 Credence Systems Corporation Method for in-line testing of semiconductor wafers
US7852094B2 (en) * 2006-12-06 2010-12-14 Formfactor, Inc. Sharing resources in a system for testing semiconductor devices
US7462038B2 (en) * 2007-02-20 2008-12-09 Qimonda Ag Interconnection structure and method of manufacturing the same
WO2010032350A1 (ja) * 2008-09-17 2010-03-25 パナソニック株式会社 半導体装置及びその製造方法
US10261123B2 (en) * 2017-08-24 2019-04-16 Micron Technology, Inc. Semiconductor device structures for burn-in testing and methods thereof

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3835530A (en) * 1967-06-05 1974-09-17 Texas Instruments Inc Method of making semiconductor devices
US3702025A (en) * 1969-05-12 1972-11-07 Honeywell Inc Discretionary interconnection process
US3803483A (en) * 1972-05-05 1974-04-09 Ibm Semiconductor structure for testing of metallization networks on insulative substrates supporting semiconductor chips
US3849872A (en) * 1972-10-24 1974-11-26 Ibm Contacting integrated circuit chip terminal through the wafer kerf
US4356379A (en) * 1978-01-13 1982-10-26 Burr-Brown Research Corporation Integrated heating element and method for thermal testing and compensation of integrated circuits
US4281449A (en) * 1979-12-21 1981-08-04 Harris Corporation Method for qualifying biased burn-in integrated circuits on a wafer level
EP0045586A3 (de) * 1980-08-02 1982-04-07 Wellman Mechanical Engineering Limited Stochvorrichtung für Gaserzeuger
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
US4467400A (en) * 1981-01-16 1984-08-21 Burroughs Corporation Wafer scale integrated circuit
US4426773A (en) * 1981-05-15 1984-01-24 General Electric Ceramics, Inc. Array of electronic packaging substrates
US4611385A (en) * 1982-06-18 1986-09-16 At&T Bell Laboratories Devices formed utilizing organic materials
JPS6065545A (ja) * 1983-09-21 1985-04-15 Hitachi Micro Comput Eng Ltd 半導体装置の製造方法
US4755750A (en) * 1985-04-08 1988-07-05 Sgs Semiconductor Corporation Wafer keys for wafer probe alignment
DE3526485A1 (de) * 1985-07-24 1987-02-05 Heinz Krug Schaltungsanordnung zum pruefen integrierter schaltungseinheiten
US4937203A (en) * 1986-09-26 1990-06-26 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
EP0286660B1 (de) * 1986-09-26 1992-03-04 General Electric Company Verfahren und anordnung zum prüfen elektronischer schaltungen und integrierter schaltungschips mit einer lösbaren bedeckungsschicht
US4801869A (en) * 1987-04-27 1989-01-31 International Business Machines Corporation Semiconductor defect monitor for diagnosing processing-induced defects
US4956602A (en) * 1989-02-14 1990-09-11 Amber Engineering, Inc. Wafer scale testing of redundant integrated circuit dies
JP2585799B2 (ja) * 1989-06-30 1997-02-26 株式会社東芝 半導体メモリ装置及びそのバーンイン方法
GB8918482D0 (en) * 1989-08-14 1989-09-20 Inmos Ltd Packaging semiconductor chips
US5037771A (en) * 1989-11-28 1991-08-06 Cross-Check Technology, Inc. Method for implementing grid-based crosscheck test structures and the structures resulting therefrom
US5059899A (en) * 1990-08-16 1991-10-22 Micron Technology, Inc. Semiconductor dies and wafers and methods for making
US5241266A (en) * 1992-04-10 1993-08-31 Micron Technology, Inc. Built-in test circuit connection for wafer level burnin and testing of individual dies

Also Published As

Publication number Publication date
US5307010A (en) 1994-04-26
KR100274558B1 (ko) 2001-01-15
EP0494782B1 (de) 1997-04-23
US5444366A (en) 1995-08-22
KR920015499A (ko) 1992-08-27
EP0494782A1 (de) 1992-07-15
US5532614A (en) 1996-07-02
DE69219165D1 (de) 1997-05-28
TW207587B (de) 1993-06-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee