DE69225463T2 - Verfahren und Gerät zur Verschachtelung von mehrkanaligen DMA-Operationen - Google Patents

Verfahren und Gerät zur Verschachtelung von mehrkanaligen DMA-Operationen

Info

Publication number
DE69225463T2
DE69225463T2 DE69225463T DE69225463T DE69225463T2 DE 69225463 T2 DE69225463 T2 DE 69225463T2 DE 69225463 T DE69225463 T DE 69225463T DE 69225463 T DE69225463 T DE 69225463T DE 69225463 T2 DE69225463 T2 DE 69225463T2
Authority
DE
Germany
Prior art keywords
dma operations
channel dma
interleaving multi
interleaving
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69225463T
Other languages
English (en)
Other versions
DE69225463D1 (de
Inventor
Martin Sodos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69225463D1 publication Critical patent/DE69225463D1/de
Application granted granted Critical
Publication of DE69225463T2 publication Critical patent/DE69225463T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
DE69225463T 1991-12-30 1992-12-07 Verfahren und Gerät zur Verschachtelung von mehrkanaligen DMA-Operationen Expired - Fee Related DE69225463T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/814,766 US5388237A (en) 1991-12-30 1991-12-30 Method of and apparatus for interleaving multiple-channel DMA operations

Publications (2)

Publication Number Publication Date
DE69225463D1 DE69225463D1 (de) 1998-06-18
DE69225463T2 true DE69225463T2 (de) 1998-12-24

Family

ID=25215954

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69225463T Expired - Fee Related DE69225463T2 (de) 1991-12-30 1992-12-07 Verfahren und Gerät zur Verschachtelung von mehrkanaligen DMA-Operationen

Country Status (5)

Country Link
US (1) US5388237A (de)
EP (1) EP0550164B1 (de)
JP (1) JP3271125B2 (de)
KR (1) KR960006503B1 (de)
DE (1) DE69225463T2 (de)

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JP2016051231A (ja) * 2014-08-29 2016-04-11 キヤノン株式会社 電子機器
KR20170024714A (ko) 2015-08-26 2017-03-08 에스케이하이닉스 주식회사 반도체 시스템 및 그의 동작 방법
US10445267B2 (en) 2016-06-29 2019-10-15 Nxp Usa, Inc. Direct memory access (DMA) unit with address alignment
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CN113360423A (zh) 2020-03-03 2021-09-07 瑞昱半导体股份有限公司 数据储存系统及操作数据储存系统的方法
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Also Published As

Publication number Publication date
JPH06266650A (ja) 1994-09-22
KR930014074A (ko) 1993-07-22
US5388237A (en) 1995-02-07
EP0550164B1 (de) 1998-05-13
KR960006503B1 (ko) 1996-05-16
DE69225463D1 (de) 1998-06-18
EP0550164A1 (de) 1993-07-07
JP3271125B2 (ja) 2002-04-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee