DE69225622D1 - Adressenübersetzungspufferspeicher mit per Eingabe veränderlicher Seitengrösse - Google Patents

Adressenübersetzungspufferspeicher mit per Eingabe veränderlicher Seitengrösse

Info

Publication number
DE69225622D1
DE69225622D1 DE69225622T DE69225622T DE69225622D1 DE 69225622 D1 DE69225622 D1 DE 69225622D1 DE 69225622 T DE69225622 T DE 69225622T DE 69225622 T DE69225622 T DE 69225622T DE 69225622 D1 DE69225622 D1 DE 69225622D1
Authority
DE
Germany
Prior art keywords
input
buffer memory
address translation
page size
translation buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69225622T
Other languages
English (en)
Other versions
DE69225622T2 (de
Inventor
Thomas J Riordan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MIPS Tech LLC
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Application granted granted Critical
Publication of DE69225622D1 publication Critical patent/DE69225622D1/de
Publication of DE69225622T2 publication Critical patent/DE69225622T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
DE69225622T 1991-01-23 1992-01-17 Adressenübersetzungspufferspeicher mit per Eingabe veränderlicher Seitengrösse Expired - Lifetime DE69225622T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/644,705 US5263140A (en) 1991-01-23 1991-01-23 Variable page size per entry translation look-aside buffer

Publications (2)

Publication Number Publication Date
DE69225622D1 true DE69225622D1 (de) 1998-07-02
DE69225622T2 DE69225622T2 (de) 1999-01-14

Family

ID=24586016

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69225622T Expired - Lifetime DE69225622T2 (de) 1991-01-23 1992-01-17 Adressenübersetzungspufferspeicher mit per Eingabe veränderlicher Seitengrösse

Country Status (4)

Country Link
US (1) US5263140A (de)
EP (1) EP0496288B1 (de)
JP (1) JP3657622B2 (de)
DE (1) DE69225622T2 (de)

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EP0508577A1 (de) * 1991-03-13 1992-10-14 International Business Machines Corporation Adressübersetzungseinrichtung
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US5617554A (en) * 1992-02-10 1997-04-01 Intel Corporation Physical address size selection and page size selection in an address translator
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US5465337A (en) * 1992-08-13 1995-11-07 Sun Microsystems, Inc. Method and apparatus for a memory management unit supporting multiple page sizes
US5574877A (en) * 1992-09-25 1996-11-12 Silicon Graphics, Inc. TLB with two physical pages per virtual tag
US5732405A (en) * 1992-10-02 1998-03-24 Motorola, Inc. Method and apparatus for performing a cache operation in a data processing system
US5442766A (en) * 1992-10-09 1995-08-15 International Business Machines Corporation Method and system for distributed instruction address translation in a multiscalar data processing system
EP0602276A1 (de) * 1992-12-18 1994-06-22 Siemens Nixdorf Informationssysteme Aktiengesellschaft Programmierbare Adre dekoder
US5568415A (en) * 1993-02-19 1996-10-22 Digital Equipment Corporation Content addressable memory having a pair of memory cells storing don't care states for address translation
US5555387A (en) * 1995-06-06 1996-09-10 International Business Machines Corporation Method and apparatus for implementing virtual memory having multiple selected page sizes
US5712998A (en) * 1993-07-13 1998-01-27 Intel Corporation Fast fully associative translation lookaside buffer with the ability to store and manage information pertaining to at least two different page sizes
US5479627A (en) * 1993-09-08 1995-12-26 Sun Microsystems, Inc. Virtual address to physical address translation cache that supports multiple page sizes
US5765209A (en) * 1993-09-23 1998-06-09 Hewlett-Packard Co. Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages
US5526503A (en) * 1993-10-06 1996-06-11 Ast Research, Inc. Virtual addressing buffer circuit
US5526504A (en) * 1993-12-15 1996-06-11 Silicon Graphics, Inc. Variable page size translation lookaside buffer
US5606683A (en) * 1994-01-28 1997-02-25 Quantum Effect Design, Inc. Structure and method for virtual-to-physical address translation in a translation lookaside buffer
US5535352A (en) * 1994-03-24 1996-07-09 Hewlett-Packard Company Access hints for input/output address translation mechanisms
DE69429503T2 (de) * 1994-03-24 2002-05-16 Hewlett Packard Co Übersetzungsmechanismus für Ein-/Ausgabeadressen
US5535351A (en) * 1994-04-04 1996-07-09 Motorola, Inc. Address translator with by-pass circuit and method of operation
US5530822A (en) * 1994-04-04 1996-06-25 Motorola, Inc. Address translator and method of operation
US5530824A (en) * 1994-04-04 1996-06-25 Motorola, Inc. Address translation circuit
US5550974A (en) * 1994-04-15 1996-08-27 Motorola, Inc. Testable memory array which is immune to multiple wordline assertions during scan testing
DE69523304T2 (de) * 1994-06-02 2002-07-11 Intel Corp Dynamischer speicher mit einem bis mehreren bits pro zelle
US5907867A (en) * 1994-09-09 1999-05-25 Hitachi, Ltd. Translation lookaside buffer supporting multiple page sizes
JP3740195B2 (ja) * 1994-09-09 2006-02-01 株式会社ルネサステクノロジ データ処理装置
DE19526960A1 (de) * 1994-09-27 1996-03-28 Hewlett Packard Co Eine Übersetzungs-Querzuordnungs-Puffer-Organisation mit variabler Seitengrößenabbildung und Opfer-Cache-Speicherung
WO1996012231A1 (en) * 1994-10-14 1996-04-25 Silicon Graphics, Inc. A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein
US5963984A (en) * 1994-11-08 1999-10-05 National Semiconductor Corporation Address translation unit employing programmable page size
US5682495A (en) * 1994-12-09 1997-10-28 International Business Machines Corporation Fully associative address translation buffer having separate segment and page invalidation
US5752275A (en) * 1995-03-31 1998-05-12 Intel Corporation Translation look-aside buffer including a single page size translation unit
US5765201A (en) * 1995-07-31 1998-06-09 International Business Machines Corporation Changing page size in storage media of computer system
EP0788113B1 (de) * 1996-01-31 2005-08-24 STMicroelectronics S.r.l. Mehrstufige Speicherschaltungen und entsprechende Lese- und Schreibverfahren
US6026476A (en) * 1996-03-19 2000-02-15 Intel Corporation Fast fully associative translation lookaside buffer
US5946716A (en) * 1996-05-30 1999-08-31 Hewlett-Packard Company Sectored virtual memory management system and translation look-aside buffer (TLB) for the same
US5875289A (en) * 1996-06-28 1999-02-23 Microsoft Corporation Method and system for simulating auto-init mode DMA data transfers
US5928352A (en) * 1996-09-16 1999-07-27 Intel Corporation Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry
US5860147A (en) * 1996-09-16 1999-01-12 Intel Corporation Method and apparatus for replacement of entries in a translation look-aside buffer
US6857099B1 (en) 1996-09-18 2005-02-15 Nippon Steel Corporation Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
KR100263672B1 (ko) * 1997-05-08 2000-09-01 김영환 가변적인 페이지 크기를 지원하는 어드레스 변환장치
US7337360B2 (en) 1999-10-19 2008-02-26 Idocrase Investments Llc Stored memory recovery system
US6594780B1 (en) 1999-10-19 2003-07-15 Inasoft, Inc. Operating system and data protection
US6647482B1 (en) * 2000-04-07 2003-11-11 Intel Corporation Method for optimized representation of page table entries
US6549997B2 (en) * 2001-03-16 2003-04-15 Fujitsu Limited Dynamic variable page size translation of addresses
US7039756B2 (en) * 2003-04-28 2006-05-02 Lsi Logic Corporation Method for use of ternary CAM to implement software programmable cache policies
US20050182903A1 (en) * 2004-02-12 2005-08-18 Mips Technologies, Inc. Apparatus and method for preventing duplicate matching entries in a translation lookaside buffer
US7558939B2 (en) 2005-03-08 2009-07-07 Mips Technologies, Inc. Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
WO2008155848A1 (ja) * 2007-06-20 2008-12-24 Fujitsu Limited 計算機、ｔｌｂ制御方法およびｔｌｂ制御プログラム
US20120124326A1 (en) * 2010-11-17 2012-05-17 Mccombs Edward M Translation Lookaside Buffer Structure Including a Data Array Sense Amplifier and Fast Compare Unit
US9086987B2 (en) * 2012-09-07 2015-07-21 International Business Machines Corporation Detection of conflicts between transactions and page shootdowns
US9086986B2 (en) * 2012-09-07 2015-07-21 International Business Machines Corporation Detection of conflicts between transactions and page shootdowns
US10901894B2 (en) 2017-03-10 2021-01-26 Oracle International Corporation Allocating and accessing memory pages with near and far memory blocks from heterogeneous memories

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FR10582E (fr) * 1970-06-29 1909-07-30 Paul Alexis Victor Lerolle Jeu de serrures avec passe-partout
US4356549A (en) * 1980-04-02 1982-10-26 Control Data Corporation System page table apparatus
US4654777A (en) * 1982-05-25 1987-03-31 Tokyo Shibaura Denki Kabushiki Kaisha Segmented one and two level paging address translation system
US4763250A (en) * 1985-04-01 1988-08-09 Motorola, Inc. Paged memory management unit having variable number of translation table levels
JPH0685156B2 (ja) * 1985-05-24 1994-10-26 株式会社日立製作所 アドレス変換装置
US4972338A (en) * 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
US4758946A (en) * 1986-04-09 1988-07-19 Elxsi Page mapping system
KR950008676B1 (ko) * 1986-04-23 1995-08-04 가부시기가이샤 히다찌세이사꾸쇼 반도체 메모리 장치 및 그의 결함 구제 방법
US5058003A (en) * 1988-12-15 1991-10-15 International Business Machines Corporation Virtual storage dynamic address translation mechanism for multiple-sized pages
US5133058A (en) * 1989-09-18 1992-07-21 Sun Microsystems, Inc. Page-tagging translation look-aside buffer for a computer memory system
CA2045789A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Granularity hint for translation buffer in high performance processor

Also Published As

Publication number Publication date
JPH0830511A (ja) 1996-02-02
EP0496288A3 (en) 1993-01-20
US5263140A (en) 1993-11-16
EP0496288B1 (de) 1998-05-27
JP3657622B2 (ja) 2005-06-08
EP0496288A2 (de) 1992-07-29
DE69225622T2 (de) 1999-01-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MIPS TECHNOLOGIES,INC., MOUNTAIN VIEW,CALIF.,, US