DE69226001D1 - Hochgeschwindigkeitsprüfung einer integrierten Schaltung mit JTAG - Google Patents

Hochgeschwindigkeitsprüfung einer integrierten Schaltung mit JTAG

Info

Publication number
DE69226001D1
DE69226001D1 DE69226001T DE69226001T DE69226001D1 DE 69226001 D1 DE69226001 D1 DE 69226001D1 DE 69226001 T DE69226001 T DE 69226001T DE 69226001 T DE69226001 T DE 69226001T DE 69226001 D1 DE69226001 D1 DE 69226001D1
Authority
DE
Germany
Prior art keywords
jtag
testing
test
speed
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69226001T
Other languages
English (en)
Other versions
DE69226001T2 (de
Inventor
Alan Joel Greenberger
Homayoon Sam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69226001D1 publication Critical patent/DE69226001D1/de
Publication of DE69226001T2 publication Critical patent/DE69226001T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
DE69226001T 1991-04-26 1992-04-14 Hochgeschwindigkeitsprüfung einer integrierten Schaltung mit JTAG Expired - Fee Related DE69226001T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/692,337 US5355369A (en) 1991-04-26 1991-04-26 High-speed integrated circuit testing with JTAG

Publications (2)

Publication Number Publication Date
DE69226001D1 true DE69226001D1 (de) 1998-07-30
DE69226001T2 DE69226001T2 (de) 1998-11-19

Family

ID=24780165

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69226001T Expired - Fee Related DE69226001T2 (de) 1991-04-26 1992-04-14 Hochgeschwindigkeitsprüfung einer integrierten Schaltung mit JTAG

Country Status (5)

Country Link
US (1) US5355369A (de)
EP (1) EP0511752B1 (de)
JP (1) JP3174617B2 (de)
DE (1) DE69226001T2 (de)
HK (1) HK1008154A1 (de)

Families Citing this family (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6704895B1 (en) * 1987-06-02 2004-03-09 Texas Instruments Incorporated Integrated circuit with emulation register in JTAG JAP
US5355369A (en) * 1991-04-26 1994-10-11 At&T Bell Laboratories High-speed integrated circuit testing with JTAG
FI93999C (fi) * 1992-06-11 1995-06-26 Nokia Mobile Phones Ltd Piirikortille asennetun mikroprosessorin ohjelmamuistin ohjelmoiminen
EP0636976B1 (de) * 1993-07-28 1998-12-30 Koninklijke Philips Electronics N.V. Mikrokontroller mit hardwaremässiger Fehlerbeseitigungsunterstützung nach dem Boundary-Scanverfahren
US6006343A (en) * 1993-07-30 1999-12-21 Texas Instruments Incorporated Method and apparatus for streamlined testing of electrical circuits
US5485466A (en) * 1993-10-04 1996-01-16 Motorola, Inc. Method and apparatus for performing dual scan path testing of an array in a data processing system
TW253031B (de) * 1993-12-27 1995-08-01 At & T Corp
US5448525A (en) * 1994-03-10 1995-09-05 Intel Corporation Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof
US5600802A (en) * 1994-03-14 1997-02-04 Apple Computer, Inc. Methods and apparatus for translating incompatible bus transactions
JP3333036B2 (ja) * 1994-03-17 2002-10-07 富士通株式会社 試験装置、試験装置を備えたシステムおよび試験方法
GB2289147B (en) * 1994-04-25 1998-04-15 Advanced Risc Mach Ltd Testing data processing apparatus
US6070252A (en) * 1994-09-30 2000-05-30 Intel Corporation Method and apparatus for interactive built-in-self-testing with user-programmable test patterns
US5479127A (en) * 1994-11-10 1995-12-26 National Semiconductor Corporation Self-resetting bypass control for scan test
JP3160480B2 (ja) * 1994-11-10 2001-04-25 株式会社東芝 半導体記憶装置
US6173428B1 (en) * 1994-11-16 2001-01-09 Cray Research, Inc. Apparatus and method for testing using clocked test access port controller for level sensitive scan designs
SE504041C2 (sv) * 1995-03-16 1996-10-21 Ericsson Telefon Ab L M Integrerat kretsarrangemang för provning
US5821773A (en) * 1995-09-06 1998-10-13 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US5748878A (en) * 1995-09-11 1998-05-05 Applied Microsystems, Inc. Method and apparatus for analyzing software executed in embedded systems
US5627840A (en) * 1995-09-15 1997-05-06 Unisys Corp. Memory based interface
US6055658A (en) * 1995-10-02 2000-04-25 International Business Machines Corporation Apparatus and method for testing high speed components using low speed test apparatus
US5640509A (en) * 1995-10-03 1997-06-17 Intel Corporation Programmable built-in self-test function for an integrated circuit
US5740353A (en) * 1995-12-14 1998-04-14 International Business Machines Corporation Method and apparatus for creating a multiprocessor verification environment
US5682391A (en) * 1996-02-22 1997-10-28 Sun Microsystems, Inc. Apparatus and method for high speed shifting of test data through an integrated circuit
US5869979A (en) * 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US5694399A (en) * 1996-04-10 1997-12-02 Xilinix, Inc. Processing unit for generating signals for communication with a test access port
US5724505A (en) * 1996-05-15 1998-03-03 Lucent Technologies Inc. Apparatus and method for real-time program monitoring via a serial interface
US5787094A (en) * 1996-06-06 1998-07-28 International Business Machines Corporation Test and diagnostics for a self-timed parallel interface
US6097211A (en) * 1996-07-18 2000-08-01 Altera Corporation Configuration memory integrated circuit
GB2346473B (en) * 1996-07-18 2000-12-27 Altera Corp Configuration memory
US5796751A (en) * 1996-07-22 1998-08-18 International Business Machines Corporation Technique for sorting high frequency integrated circuits
GB9617033D0 (en) * 1996-08-14 1996-09-25 Int Computers Ltd Diagnostic memory access
US5768152A (en) * 1996-08-28 1998-06-16 International Business Machines Corp. Performance monitoring through JTAG 1149.1 interface
US6324662B1 (en) * 1996-08-30 2001-11-27 Texas Instruments Incorporated TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports
US5805607A (en) * 1996-10-22 1998-09-08 Advanced Micro Devices, Inc. Method for user-controlled I/O switching during in-circuit programming of CPLDs through the IEEE 1149.1 test access port
US5701308A (en) * 1996-10-29 1997-12-23 Lockheed Martin Corporation Fast bist architecture with flexible standard interface
US5983017A (en) * 1996-11-12 1999-11-09 Lsi Logic Corporation Virtual monitor debugging method and apparatus
US6142683A (en) * 1997-04-08 2000-11-07 Advanced Micro Devices, Inc. Debug interface including data steering between a processor, an input/output port, and a trace logic
US6189140B1 (en) 1997-04-08 2001-02-13 Advanced Micro Devices, Inc. Debug interface including logic generating handshake signals between a processor, an input/output port, and a trace logic
US6148381A (en) * 1997-04-08 2000-11-14 Advanced Micro Devices, Inc. Single-port trace buffer architecture with overflow reduction
US6041406A (en) * 1997-04-08 2000-03-21 Advanced Micro Devices, Inc. Parallel and serial debug port on a processor
US6154856A (en) * 1997-04-08 2000-11-28 Advanced Micro Devices, Inc. Debug interface including state machines for timing synchronization and communication
US6044481A (en) * 1997-05-09 2000-03-28 Artisan Components, Inc. Programmable universal test interface for testing memories with different test methodologies
US5968192A (en) * 1997-05-09 1999-10-19 Artisan Components, Inc. Programmable universal test interface and method for making the same
US6118622A (en) * 1997-05-13 2000-09-12 International Business Machines Corporation Technique for robust resetting of spin valve head
US6421812B1 (en) 1997-06-10 2002-07-16 Altera Corporation Programming mode selection with JTAG circuits
US6691267B1 (en) 1997-06-10 2004-02-10 Altera Corporation Technique to test an integrated circuit using fewer pins
US6539510B1 (en) 1997-08-12 2003-03-25 Xilinx, Inc. Interface board for receiving modular interface cards
US6618775B1 (en) 1997-08-15 2003-09-09 Micron Technology, Inc. DSP bus monitoring apparatus and method
US6279123B1 (en) * 1997-09-15 2001-08-21 Lucent Technologies, Inc. System for viewing and monitoring embedded processor operation
KR100240662B1 (ko) * 1997-09-25 2000-01-15 윤종용 제이태그에 의한 다이나믹램 테스트장치
US6125464A (en) * 1997-10-16 2000-09-26 Adaptec, Inc. High speed boundary scan design
US6141790A (en) * 1997-10-30 2000-10-31 Synopsys, Inc. Instructions signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker
US6032279A (en) * 1997-11-07 2000-02-29 Atmel Corporation Boundary scan system with address dependent instructions
US5920765A (en) * 1997-12-12 1999-07-06 Naum; Michael IC wafer-probe testable flip-chip architecture
US6014763A (en) * 1998-01-15 2000-01-11 International Business Machines Corporation At-speed scan testing
US6106571A (en) * 1998-01-29 2000-08-22 Applied Microsystems Corporation Relocatable instrumentation tags for testing and debugging a computer program
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6145100A (en) * 1998-03-04 2000-11-07 Advanced Micro Devices, Inc. Debug interface including timing synchronization logic
KR100512162B1 (ko) * 1998-03-31 2005-11-11 삼성전자주식회사 마이크로프로세서의에뮬레이션모드를위한바운더리스캔스탠다드인터페이스회로
US6145122A (en) * 1998-04-27 2000-11-07 Motorola, Inc. Development interface for a data processor
JPH11328972A (ja) 1998-05-18 1999-11-30 Mitsubishi Electric Corp 半導体装置、その設計方法およびその検査方法
US6243842B1 (en) * 1998-06-08 2001-06-05 Stmicroelectronics, Inc. Method and apparatus for operating on a memory unit via a JTAG port
JP2000011691A (ja) * 1998-06-16 2000-01-14 Mitsubishi Electric Corp 半導体試験装置
US6966021B2 (en) * 1998-06-16 2005-11-15 Janusz Rajski Method and apparatus for at-speed testing of digital circuits
US6151693A (en) * 1998-06-19 2000-11-21 Lucent Technologies, Inc. Automated method of burn-in and endurance testing for embedded EEPROM
US6560734B1 (en) * 1998-06-19 2003-05-06 Texas Instruments Incorporated IC with addressable test port
US6145123A (en) * 1998-07-01 2000-11-07 Advanced Micro Devices, Inc. Trace on/off with breakpoint register
JP2000029736A (ja) * 1998-07-13 2000-01-28 Oki Electric Ind Co Ltd 半導体集積回路
DE19835258B4 (de) * 1998-08-04 2006-07-27 Infineon Technologies Ag Integrierte dynamische Speicherschaltung mit einer Selbsttesteinrichtung
JP2000065899A (ja) * 1998-08-14 2000-03-03 Sony Corp 半導体装置およびそのデータ書き換え方法
US6100743A (en) * 1998-08-25 2000-08-08 Lucent Technologies Inc. Circuit arrangement for adding functionality to a circuit with reduced propagation delays
US6266801B1 (en) * 1998-09-15 2001-07-24 Adaptec, Inc. Boundary-scan cells with improved timing characteristics
US6184707B1 (en) 1998-10-07 2001-02-06 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US6347387B1 (en) 1998-10-09 2002-02-12 Agere Systems Guardian Corp. Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links
US6256760B1 (en) 1998-11-13 2001-07-03 Nortel Networks Limited Automatic test equipment scan test enhancement
GB2344184A (en) * 1998-11-26 2000-05-31 Ericsson Telefon Ab L M Testing integrated circuits
US6449738B1 (en) 1998-12-03 2002-09-10 International Business Machines Corporation Apparatus for bus frequency independent wrap I/O testing and method therefor
US6246971B1 (en) * 1999-01-05 2001-06-12 Lucent Technologies Inc. Testing asynchronous circuits
US6349398B1 (en) 1999-01-26 2002-02-19 Silicon Graphics, Inc. Method and apparatus for partial-scan built-in self test logic
US6427216B1 (en) 1999-03-11 2002-07-30 Agere Systems Guardian Corp. Integrated circuit testing using a high speed data interface bus
DE19930169B4 (de) 1999-06-30 2004-09-30 Infineon Technologies Ag Testeinrichtung und Verfahren zum Prüfen eines Speichers
US6430718B1 (en) 1999-08-30 2002-08-06 Cypress Semiconductor Corp. Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom
US6367032B1 (en) * 1999-10-21 2002-04-02 Sony Corporation Of Japan Method and system for debugging a microprocessor core
US6973417B1 (en) 1999-11-05 2005-12-06 Metrowerks Corporation Method and system for simulating execution of a target program in a simulated target system
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6598193B1 (en) 2000-01-24 2003-07-22 Dell Products L.P. System and method for testing component IC chips
US6769080B2 (en) * 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6804802B1 (en) * 2000-06-22 2004-10-12 Cypress Semiconductor Corp. JTAG instruction register and decoder for PLDS
US6640324B1 (en) 2000-08-07 2003-10-28 Agere Systems Inc. Boundary scan chain routing
US6681359B1 (en) 2000-08-07 2004-01-20 Cypress Semiconductor Corp. Semiconductor memory self-test controllable at board level using standard interface
US6766486B2 (en) * 2000-12-05 2004-07-20 Intel Corporation Joint test action group (JTAG) tester, such as to test integrated circuits in parallel
US6865701B1 (en) * 2001-03-29 2005-03-08 Apple Computer, Inc. Method and apparatus for improved memory core testing
US7065675B1 (en) * 2001-05-08 2006-06-20 Mips Technologies, Inc. System and method for speeding up EJTAG block data transfers
US7401271B1 (en) * 2001-08-20 2008-07-15 Emc Corporation Testing system and method of using same
US6918057B1 (en) * 2001-08-24 2005-07-12 Cypress Semiconductor Corp. Architecture, circuitry and method for controlling a subsystem through a JTAG access port
US7428661B2 (en) * 2001-09-21 2008-09-23 Sam Michael Test and debug processor and method
WO2003034202A2 (en) * 2001-10-17 2003-04-24 Koninklijke Philips Electronics N.V. On the fly configuration of electronic device with attachable sub-modules
US20030084390A1 (en) * 2001-10-26 2003-05-01 Mentor Graphics Corporation At-speed test using on-chip controller
FR2831969B1 (fr) * 2001-11-08 2004-01-16 Schneider Automation Systeme de telechargement et de telemaintenance d'une carte electronique
US7185251B2 (en) * 2002-05-29 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for affecting a portion of an integrated circuit
US7131033B1 (en) * 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
FR2843201A1 (fr) * 2002-08-02 2004-02-06 St Microelectronics Sa Procede pour deboguer un microprogramme, et dispositif de developpement de composant electronique.
US7356369B2 (en) * 2003-10-02 2008-04-08 Medtronic, Inc. Z-axis assembly of medical device programmer
US20050159925A1 (en) * 2004-01-15 2005-07-21 Elias Gedamu Cache testing for a processor design
US20050172178A1 (en) * 2004-01-15 2005-08-04 Elias Gedamu Cache-testable processor identification
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
US20060125508A1 (en) * 2004-12-15 2006-06-15 Impinj, Inc. On wafer testing of RFID tag circuit with pseudo antenna signal
US7380190B2 (en) * 2004-12-15 2008-05-27 Impinj, Inc. RFID tag with bist circuits
US7307528B2 (en) * 2004-12-15 2007-12-11 Impinj, Inc. RFID tag design with circuitry for wafer level testing
US7400255B2 (en) * 2005-02-28 2008-07-15 Impinj, Inc. Wireless functional testing of RFID tag
US7528724B2 (en) * 2005-02-28 2009-05-05 Impinj, Inc. On die RFID tag antenna
JP2006329810A (ja) * 2005-05-26 2006-12-07 Nec Electronics Corp 半導体集積回路及びそのテスト方法
US7587643B1 (en) 2005-08-25 2009-09-08 T-Ram Semiconductor, Inc. System and method of integrated circuit testing
US20080005634A1 (en) * 2006-06-29 2008-01-03 Grise Gary D Scan chain circuitry that enables scan testing at functional clock speed
US7689866B2 (en) * 2006-10-18 2010-03-30 Alcatel-Lucent Usa Inc. Method and apparatus for injecting transient hardware faults for software testing
US7707467B2 (en) * 2007-02-23 2010-04-27 Micron Technology, Inc. Input/output compression and pin reduction in an integrated circuit
US7685484B2 (en) * 2007-11-14 2010-03-23 International Business Machines Corporation Methods for the support of JTAG for source synchronous interfaces
JP2010159989A (ja) * 2009-01-06 2010-07-22 Renesas Electronics Corp テスト回路
US20130086441A1 (en) * 2011-09-30 2013-04-04 Qualcomm Incorporated Dynamically self-reconfigurable daisy-chain of tap controllers
US8904255B2 (en) * 2012-02-21 2014-12-02 Lsi Corporation Integrated circuit having clock gating circuitry responsive to scan shift control signal
TWI483256B (zh) * 2012-10-18 2015-05-01 Inventec Corp 提高邊界掃描技術對晶片燒錄速度的系統及其方法
US9482718B2 (en) * 2014-01-13 2016-11-01 Texas Instruments Incorporated Integrated circuit
US10902933B2 (en) * 2018-08-31 2021-01-26 Nvidia Corporation Test system for executing built-in self-test in deployment for automotive applications
US11009547B2 (en) * 2018-12-06 2021-05-18 Super Micro Computer, Inc. Device and method for testing a computer system
US10746798B1 (en) 2019-05-31 2020-08-18 Nvidia Corp. Field adaptable in-system test mechanisms
US11204849B2 (en) * 2020-03-13 2021-12-21 Nvidia Corporation Leveraging low power states for fault testing of processing cores at runtime
CN113219940A (zh) * 2021-04-08 2021-08-06 新风光电子科技股份有限公司 一台电脑控制多测试站的fct测试系统及控制方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455661A (en) * 1980-04-03 1984-06-19 Codex Corporation Dual processor digital modem apparatus
JPS6298437A (ja) * 1985-10-24 1987-05-07 Oki Electric Ind Co Ltd マイクロコンピユ−タ
US4710927A (en) * 1986-07-24 1987-12-01 Integrated Device Technology, Inc. Diagnostic circuit
US4811345A (en) * 1986-12-16 1989-03-07 Advanced Micro Devices, Inc. Methods and apparatus for providing a user oriented microprocessor test interface for a complex, single chip, general purpose central processing unit
US4945536A (en) * 1988-09-09 1990-07-31 Northern Telecom Limited Method and apparatus for testing digital systems
JP2518039B2 (ja) * 1989-03-06 1996-07-24 日本電気株式会社 デ―タ処理装置の制御記憶ロ―ド方法
US5355369A (en) * 1991-04-26 1994-10-11 At&T Bell Laboratories High-speed integrated circuit testing with JTAG

Also Published As

Publication number Publication date
JPH05164826A (ja) 1993-06-29
JP3174617B2 (ja) 2001-06-11
EP0511752B1 (de) 1998-06-24
EP0511752A1 (de) 1992-11-04
DE69226001T2 (de) 1998-11-19
US5355369A (en) 1994-10-11
HK1008154A1 (en) 1999-04-30

Similar Documents

Publication Publication Date Title
DE69226001T2 (de) Hochgeschwindigkeitsprüfung einer integrierten Schaltung mit JTAG
US9575121B2 (en) Off-chip tap interface control with instruction register, multiplexer and buffer
US5608736A (en) Method and apparatus for a universal programmable boundary scan driver/sensor circuit
US9817071B2 (en) TDI/TMS DDR coupled JTAG domain with 6 preset flip flops
US5670890A (en) Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
US6658632B1 (en) Boundary scan cell architecture with complete set of operational modes for high performance integrated circuits
EP0388001A3 (de) Prüfverfahren und -gerät für integrierte Schaltungen
US7269770B1 (en) AC coupled line testing using boundary scan test methodology
EP0548585A3 (de)
KR950033511A (ko) 장치의 경계-탐색 포트를 사용해서 그 장치를 부분 · 탐색 검사하는 방법
US5644251A (en) Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
US6877121B1 (en) Boundary scan cell for testing AC coupled line using phase modulation technique
US5828827A (en) Data processing system for performing a test function and method therefor
DE69229362D1 (de) Schaltung zur Erzeugung künstlicher Zufallszahlenmuster
US4916388A (en) Semiconductor integrated circuit device equipped with scan-pass type test circuit
EP0685075B1 (de) Anordnung zum testen von verbindungen mit pulling-widerständen
US6061284A (en) Core test control
DE69030209T2 (de) Durch Ereigniss befähigte Prüfarchitektur für integrierte Schaltungen
CA1296110C (en) Reconfigurable register bit-slice for self-test
US6988207B2 (en) Scan insertion testing of ASICs
Wu et al. Interconnect delay fault testing with IEEE 1149.1
Andrews IEEE: 1141.1 applied to mixed TTL-ECL and differentlal logic
JP3228875B2 (ja) 信号配線の接続テスト方法、テスト装置及びバウンダリスキャン対応のｉｃ
KR940002724Y1 (ko) 다중핀 디지탈 ic 시험회로
JP2820975B2 (ja) 大規模集積回路のスキャンテスト方法

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee