DE69230229D1 - Verfahren für die Ätzung und/oder Einebung eines mehrschichtigen Halbleitersubstrats - Google Patents

Verfahren für die Ätzung und/oder Einebung eines mehrschichtigen Halbleitersubstrats

Info

Publication number
DE69230229D1
DE69230229D1 DE69230229T DE69230229T DE69230229D1 DE 69230229 D1 DE69230229 D1 DE 69230229D1 DE 69230229 T DE69230229 T DE 69230229T DE 69230229 T DE69230229 T DE 69230229T DE 69230229 D1 DE69230229 D1 DE 69230229D1
Authority
DE
Germany
Prior art keywords
leveling
etching
semiconductor substrate
multilayer semiconductor
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69230229T
Other languages
English (en)
Other versions
DE69230229T2 (de
Inventor
Fumihide Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69230229D1 publication Critical patent/DE69230229D1/de
Application granted granted Critical
Publication of DE69230229T2 publication Critical patent/DE69230229T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
DE69230229T 1991-01-09 1992-01-06 Verfahren für die Ätzung und/oder Einebung eines mehrschichtigen Halbleitersubstrats Expired - Fee Related DE69230229T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3000795A JPH0645327A (ja) 1991-01-09 1991-01-09 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69230229D1 true DE69230229D1 (de) 1999-12-09
DE69230229T2 DE69230229T2 (de) 2000-02-17

Family

ID=11483617

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69230229T Expired - Fee Related DE69230229T2 (de) 1991-01-09 1992-01-06 Verfahren für die Ätzung und/oder Einebung eines mehrschichtigen Halbleitersubstrats

Country Status (4)

Country Link
US (1) US5272115A (de)
EP (1) EP0494745B1 (de)
JP (1) JPH0645327A (de)
DE (1) DE69230229T2 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384483A (en) * 1992-02-28 1995-01-24 Sgs-Thomson Microelectronics, Inc. Planarizing glass layer spaced from via holes
JP2820187B2 (ja) * 1992-04-16 1998-11-05 三星電子 株式会社 半導体装置の製造方法
US5419803A (en) * 1993-11-17 1995-05-30 Hughes Aircraft Company Method of planarizing microstructures
US5488015A (en) * 1994-05-20 1996-01-30 Texas Instruments Incorporated Method of making an interconnect structure with an integrated low density dielectric
US5494854A (en) * 1994-08-17 1996-02-27 Texas Instruments Incorporated Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films
US5670828A (en) * 1995-02-21 1997-09-23 Advanced Micro Devices, Inc. Tunneling technology for reducing intra-conductive layer capacitance
US5672907A (en) * 1995-03-22 1997-09-30 Nippon Steel Corporation Semiconductor device having character in BPSG film
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas
US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
KR100190048B1 (ko) * 1996-06-25 1999-06-01 윤종용 반도체 소자의 소자 분리 방법
US6115233A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region
US6395620B1 (en) * 1996-10-08 2002-05-28 Micron Technology, Inc. Method for forming a planar surface over low density field areas on a semiconductor wafer
US6108093A (en) * 1997-06-04 2000-08-22 Lsi Logic Corporation Automated inspection system for residual metal after chemical-mechanical polishing
JPH1187286A (ja) 1997-09-05 1999-03-30 Lsi Logic Corp 半導体ウエハの二段階式化学的機械的研磨方法及び装置
US6234883B1 (en) 1997-10-01 2001-05-22 Lsi Logic Corporation Method and apparatus for concurrent pad conditioning and wafer buff in chemical mechanical polishing
EP0932191A1 (de) * 1997-12-30 1999-07-28 International Business Machines Corporation Plasmaätzverfahren von dotierten Polysilizium Schichten mit gleichmässigen Ätzgeschwindigkeiten
US6531397B1 (en) 1998-01-09 2003-03-11 Lsi Logic Corporation Method and apparatus for using across wafer back pressure differentials to influence the performance of chemical mechanical polishing
US6060370A (en) * 1998-06-16 2000-05-09 Lsi Logic Corporation Method for shallow trench isolations with chemical-mechanical polishing
US6071818A (en) 1998-06-30 2000-06-06 Lsi Logic Corporation Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material
US6241847B1 (en) 1998-06-30 2001-06-05 Lsi Logic Corporation Method and apparatus for detecting a polishing endpoint based upon infrared signals
US6077783A (en) * 1998-06-30 2000-06-20 Lsi Logic Corporation Method and apparatus for detecting a polishing endpoint based upon heat conducted through a semiconductor wafer
US6268224B1 (en) 1998-06-30 2001-07-31 Lsi Logic Corporation Method and apparatus for detecting an ion-implanted polishing endpoint layer within a semiconductor wafer
US6285035B1 (en) 1998-07-08 2001-09-04 Lsi Logic Corporation Apparatus for detecting an endpoint polishing layer of a semiconductor wafer having a wafer carrier with independent concentric sub-carriers and associated method
US6074517A (en) * 1998-07-08 2000-06-13 Lsi Logic Corporation Method and apparatus for detecting an endpoint polishing layer by transmitting infrared light signals through a semiconductor wafer
US6066266A (en) * 1998-07-08 2000-05-23 Lsi Logic Corporation In-situ chemical-mechanical polishing slurry formulation for compensation of polish pad degradation
US6080670A (en) * 1998-08-10 2000-06-27 Lsi Logic Corporation Method of detecting a polishing endpoint layer of a semiconductor wafer which includes a non-reactive reporting specie
US6201253B1 (en) 1998-10-22 2001-03-13 Lsi Logic Corporation Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system
US6225210B1 (en) * 1998-12-09 2001-05-01 Advanced Micro Devices, Inc. High density capping layers with improved adhesion to copper interconnects
US6121147A (en) * 1998-12-11 2000-09-19 Lsi Logic Corporation Apparatus and method of detecting a polishing endpoint layer of a semiconductor wafer which includes a metallic reporting substance
US6117779A (en) 1998-12-15 2000-09-12 Lsi Logic Corporation Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint
US6528389B1 (en) 1998-12-17 2003-03-04 Lsi Logic Corporation Substrate planarization with a chemical mechanical polishing stop layer
US7751609B1 (en) 2000-04-20 2010-07-06 Lsi Logic Corporation Determination of film thickness during chemical mechanical polishing
KR100856325B1 (ko) * 2005-12-29 2008-09-03 동부일렉트로닉스 주식회사 반도체 소자의 절연막 및 그 형성 방법
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57102051A (en) * 1980-12-17 1982-06-24 Fujitsu Ltd Manufacture of semiconductor device
JPS59147433A (ja) * 1983-02-14 1984-08-23 Hitachi Ltd エツチング装置
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
JPS61194748A (ja) * 1985-02-25 1986-08-29 Hitachi Ltd 半導体集積回路装置の製造方法
US4752129A (en) * 1985-03-27 1988-06-21 Anritsu Corporation Wavelength modulation derivative spectrometer
JPS6273723A (ja) * 1985-09-27 1987-04-04 Sumitomo Electric Ind Ltd エツチバツク法による平坦化工程終点検出方法
JPS63107026A (ja) * 1986-10-23 1988-05-12 Tokuda Seisakusho Ltd プラズマエツチング装置
JPH0194623A (ja) * 1987-10-06 1989-04-13 Nec Corp 多層配線半導体装置の製造方法
GB2211348A (en) * 1987-10-16 1989-06-28 Philips Nv A method of forming an interconnection between conductive levels
DE3801976A1 (de) * 1988-01-23 1989-08-03 Telefunken Electronic Gmbh Verfahren zum planarisieren von halbleiteroberflaechen
GB2216336A (en) * 1988-03-30 1989-10-04 Philips Nv Forming insulating layers on substrates
US4975141A (en) * 1990-03-30 1990-12-04 International Business Machines Corporation Laser ablation for plasma etching endpoint detection
US5169491A (en) * 1991-07-29 1992-12-08 Micron Technology, Inc. Method of etching SiO2 dielectric layers using chemical mechanical polishing techniques

Also Published As

Publication number Publication date
EP0494745A2 (de) 1992-07-15
US5272115A (en) 1993-12-21
EP0494745B1 (de) 1999-11-03
DE69230229T2 (de) 2000-02-17
JPH0645327A (ja) 1994-02-18
EP0494745A3 (de) 1994-03-16

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8339 Ceased/non-payment of the annual fee