DE69230458T2 - Halbleiterkörper, Verfahren zu seiner Herstellung und Halbleiteranordnung mit diesem Körper - Google Patents
Halbleiterkörper, Verfahren zu seiner Herstellung und Halbleiteranordnung mit diesem KörperInfo
- Publication number
- DE69230458T2 DE69230458T2 DE69230458T DE69230458T DE69230458T2 DE 69230458 T2 DE69230458 T2 DE 69230458T2 DE 69230458 T DE69230458 T DE 69230458T DE 69230458 T DE69230458 T DE 69230458T DE 69230458 T2 DE69230458 T2 DE 69230458T2
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor
- production
- arrangement
- semiconductor arrangement
- semiconductor body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3253899A JP3017860B2 (ja) | 1991-10-01 | 1991-10-01 | 半導体基体およびその製造方法とその半導体基体を用いた半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69230458D1 DE69230458D1 (de) | 2000-01-27 |
DE69230458T2 true DE69230458T2 (de) | 2000-07-13 |
Family
ID=17257635
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69230458T Expired - Lifetime DE69230458T2 (de) | 1991-10-01 | 1992-10-01 | Halbleiterkörper, Verfahren zu seiner Herstellung und Halbleiteranordnung mit diesem Körper |
Country Status (5)
Country | Link |
---|---|
US (1) | US5384473A (de) |
EP (1) | EP0535681B1 (de) |
JP (1) | JP3017860B2 (de) |
KR (1) | KR960008733B1 (de) |
DE (1) | DE69230458T2 (de) |
Families Citing this family (78)
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---|---|---|---|---|
JP2605597B2 (ja) * | 1993-09-09 | 1997-04-30 | 日本電気株式会社 | 半導体装置の製造方法 |
US5698893A (en) * | 1995-01-03 | 1997-12-16 | Motorola, Inc. | Static-random-access memory cell with trench transistor and enhanced stability |
US5994188A (en) * | 1996-04-15 | 1999-11-30 | Delco Electronics Corporation | Method of fabricating a vertical power device with integrated control circuitry |
KR100223915B1 (ko) * | 1996-10-22 | 1999-10-15 | 구본준 | 반도체 소자의 구조 및 제조방법 |
KR100486191B1 (ko) | 1997-05-15 | 2005-05-03 | 지멘스 악티엔게젤샤프트 | 집적 cmos-회로 및 상기 회로의 제조 방법 |
KR100344818B1 (ko) * | 1997-09-24 | 2002-11-18 | 주식회사 하이닉스반도체 | 반도체소자및그의제조방법 |
JP4521542B2 (ja) * | 1999-03-30 | 2010-08-11 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体基板 |
US6483171B1 (en) * | 1999-08-13 | 2002-11-19 | Micron Technology, Inc. | Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same |
US6861326B2 (en) * | 2001-11-21 | 2005-03-01 | Micron Technology, Inc. | Methods of forming semiconductor circuitry |
US6967351B2 (en) * | 2001-12-04 | 2005-11-22 | International Business Machines Corporation | Finfet SRAM cell using low mobility plane for cell stability and method for forming |
JP4265882B2 (ja) | 2001-12-13 | 2009-05-20 | 忠弘 大見 | 相補型mis装置 |
US20050013996A1 (en) * | 2002-03-08 | 2005-01-20 | Hatfield Stephen F. | Hot melt pressure sensitive adhesives for disposable articles |
KR100450683B1 (ko) * | 2002-09-04 | 2004-10-01 | 삼성전자주식회사 | Soi 기판에 형성되는 에스램 디바이스 |
US6902962B2 (en) * | 2003-04-04 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-on-insulator chip with multiple crystal orientations |
JP4700264B2 (ja) * | 2003-05-21 | 2011-06-15 | 財団法人国際科学振興財団 | 半導体装置 |
US7329923B2 (en) * | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
US6821826B1 (en) * | 2003-09-30 | 2004-11-23 | International Business Machines Corporation | Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers |
CN100361302C (zh) * | 2003-10-29 | 2008-01-09 | 国际商业机器公司 | 混合衬底、集成半导体结构以及它们的制备方法 |
US7319258B2 (en) * | 2003-10-31 | 2008-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip with<100>-oriented transistors |
US20050116290A1 (en) * | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
US20050224797A1 (en) * | 2004-04-01 | 2005-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS fabricated on different crystallographic orientation substrates |
US7208815B2 (en) * | 2004-05-28 | 2007-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof |
US7291886B2 (en) * | 2004-06-21 | 2007-11-06 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
DE102004031708B4 (de) * | 2004-06-30 | 2008-02-07 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Herstellen eines Substrats mit kristallinen Halbleitergebieten unterschiedlicher Eigenschaften |
US7094634B2 (en) * | 2004-06-30 | 2006-08-22 | International Business Machines Corporation | Structure and method for manufacturing planar SOI substrate with multiple orientations |
US7186622B2 (en) * | 2004-07-15 | 2007-03-06 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
JP2006040911A (ja) * | 2004-07-22 | 2006-02-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7253034B2 (en) * | 2004-07-29 | 2007-08-07 | International Business Machines Corporation | Dual SIMOX hybrid orientation technology (HOT) substrates |
US7348658B2 (en) * | 2004-08-30 | 2008-03-25 | International Business Machines Corporation | Multilayer silicon over insulator device |
WO2006038305A1 (ja) | 2004-10-01 | 2006-04-13 | Tadahiro Ohmi | 半導体装置およびその製造方法 |
US7439542B2 (en) * | 2004-10-05 | 2008-10-21 | International Business Machines Corporation | Hybrid orientation CMOS with partial insulation process |
CN100423265C (zh) * | 2004-10-15 | 2008-10-01 | 中国科学院上海微系统与信息技术研究所 | 三维互补金属氧化物半导体晶体管的制备方法 |
DE102004064248B3 (de) * | 2004-11-30 | 2015-05-07 | Advanced Micro Devices, Inc. | Substrat mit kristallinen Halbleitergebieten mit unterschiedlichen Eigenschaften |
DE102004057764B4 (de) * | 2004-11-30 | 2013-05-16 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung eines Substrats mit kristallinen Halbleitergebieten mit unterschiedlichen Eigenschaften, die über einem kristallinen Vollsubstrat angeordnet sind und damit hergestelltes Halbleiterbauelement |
DE102004060961B4 (de) * | 2004-12-17 | 2010-06-02 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines Hybridhalbleitersubstrats über einer vergrabenen Isolierschicht |
US7298009B2 (en) * | 2005-02-01 | 2007-11-20 | Infineon Technologies Ag | Semiconductor method and device with mixed orientation substrate |
US7268377B2 (en) * | 2005-02-25 | 2007-09-11 | International Business Machines Corporation | Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices |
US6972478B1 (en) * | 2005-03-07 | 2005-12-06 | Advanced Micro Devices, Inc. | Integrated circuit and method for its manufacture |
US7288821B2 (en) * | 2005-04-08 | 2007-10-30 | International Business Machines Corporation | Structure and method of three dimensional hybrid orientation technology |
US7605429B2 (en) * | 2005-04-15 | 2009-10-20 | International Business Machines Corporation | Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement |
US20090072243A1 (en) * | 2005-04-18 | 2009-03-19 | Kyoto University | Compound semiconductor device and method for fabricating compound semiconductor |
US7291539B2 (en) | 2005-06-01 | 2007-11-06 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
US20060272574A1 (en) * | 2005-06-07 | 2006-12-07 | Advanced Micro Devices, Inc. | Methods for manufacturing integrated circuits |
US7432149B2 (en) * | 2005-06-23 | 2008-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS on SOI substrates with hybrid crystal orientations |
US7611937B2 (en) * | 2005-06-24 | 2009-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance transistors with hybrid crystal orientations |
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US7250656B2 (en) * | 2005-08-19 | 2007-07-31 | International Business Machines Corporation | Hybrid-orientation technology buried n-well design |
US7737532B2 (en) * | 2005-09-06 | 2010-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid Schottky source-drain CMOS for high mobility and low barrier |
US7605447B2 (en) * | 2005-09-22 | 2009-10-20 | International Business Machines Corporation | Highly manufacturable SRAM cells in substrates with hybrid crystal orientation |
JP2007134593A (ja) * | 2005-11-11 | 2007-05-31 | Fujio Masuoka | 半導体装置およびその製造方法 |
US7288458B2 (en) * | 2005-12-14 | 2007-10-30 | Freescale Semiconductor, Inc. | SOI active layer with different surface orientation |
US8530355B2 (en) * | 2005-12-23 | 2013-09-10 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
US20070145367A1 (en) * | 2005-12-27 | 2007-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit structure |
US7709303B2 (en) * | 2006-01-10 | 2010-05-04 | Freescale Semiconductor, Inc. | Process for forming an electronic device including a fin-type structure |
US7754560B2 (en) * | 2006-01-10 | 2010-07-13 | Freescale Semiconductor, Inc. | Integrated circuit using FinFETs and having a static random access memory (SRAM) |
US7723805B2 (en) * | 2006-01-10 | 2010-05-25 | Freescale Semiconductor, Inc. | Electronic device including a fin-type transistor structure and a process for forming the electronic device |
US7414877B2 (en) * | 2006-01-23 | 2008-08-19 | Freescale Semiconductor, Inc. | Electronic device including a static-random-access memory cell and a process of forming the electronic device |
US20070190795A1 (en) * | 2006-02-13 | 2007-08-16 | Haoren Zhuang | Method for fabricating a semiconductor device with a high-K dielectric |
US7754587B2 (en) * | 2006-03-14 | 2010-07-13 | Freescale Semiconductor, Inc. | Silicon deposition over dual surface orientation substrates to promote uniform polishing |
US7456055B2 (en) | 2006-03-15 | 2008-11-25 | Freescale Semiconductor, Inc. | Process for forming an electronic device including semiconductor fins |
US7419866B2 (en) * | 2006-03-15 | 2008-09-02 | Freescale Semiconductor, Inc. | Process of forming an electronic device including a semiconductor island over an insulating layer |
US7396407B2 (en) * | 2006-04-18 | 2008-07-08 | International Business Machines Corporation | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates |
JP4143096B2 (ja) | 2006-04-25 | 2008-09-03 | 株式会社東芝 | Mos型半導体装置及びその製造方法 |
DE102006019835B4 (de) * | 2006-04-28 | 2011-05-12 | Advanced Micro Devices, Inc., Sunnyvale | Transistor mit einem Kanal mit Zugverformung, der entlang einer kristallographischen Orientierung mit erhöhter Ladungsträgerbeweglichkeit orientiert ist |
WO2008005026A1 (en) * | 2006-07-07 | 2008-01-10 | International Business Machines Corporation | Method and apparatus for improving integrate circuit device performance using hydrid crystal orientations |
US7595232B2 (en) * | 2006-09-07 | 2009-09-29 | International Business Machines Corporation | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors |
US7750406B2 (en) * | 2007-04-20 | 2010-07-06 | International Business Machines Corporation | Design structure incorporating a hybrid substrate |
KR101461206B1 (ko) * | 2007-05-17 | 2014-11-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체장치 및 그의 제조방법 |
EP2065921A1 (de) | 2007-11-29 | 2009-06-03 | S.O.I.T.E.C. Silicon on Insulator Technologies | Verfahren zur Herstellung eines Halbleitersubstrats mit Bereichen verschiedener Kristallorientierung |
US9059282B2 (en) | 2007-12-03 | 2015-06-16 | Infineon Technologies Ag | Semiconductor devices having transistors along different orientations |
US8211786B2 (en) * | 2008-02-28 | 2012-07-03 | International Business Machines Corporation | CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication |
FR2935539B1 (fr) * | 2008-08-26 | 2010-12-10 | Commissariat Energie Atomique | Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation |
TWI406362B (zh) * | 2009-11-19 | 2013-08-21 | Univ Nat United | A complementary gold - oxygen - semi - crystal system method for increasing the mobility of holes in PMOS element region |
US20120080777A1 (en) * | 2010-09-30 | 2012-04-05 | Toshiba America Electronic Components, Inc. | Triple oxidation on dsb substrate |
US8815699B2 (en) * | 2012-11-07 | 2014-08-26 | Globalfoundries Inc. | Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells |
US10593600B2 (en) | 2016-02-24 | 2020-03-17 | International Business Machines Corporation | Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap |
US10062693B2 (en) * | 2016-02-24 | 2018-08-28 | International Business Machines Corporation | Patterned gate dielectrics for III-V-based CMOS circuits |
US9871050B1 (en) | 2016-08-10 | 2018-01-16 | Globalfoundries Inc. | Flash memory device |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3476991A (en) * | 1967-11-08 | 1969-11-04 | Texas Instruments Inc | Inversion layer field effect device with azimuthally dependent carrier mobility |
US3612960A (en) * | 1968-10-15 | 1971-10-12 | Tokyo Shibaura Electric Co | Semiconductor device |
US3634737A (en) * | 1969-02-07 | 1972-01-11 | Tokyo Shibaura Electric Co | Semiconductor device |
US3603848A (en) * | 1969-02-27 | 1971-09-07 | Tokyo Shibaura Electric Co | Complementary field-effect-type semiconductor device |
JPS60154548A (ja) * | 1984-01-24 | 1985-08-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US4768076A (en) * | 1984-09-14 | 1988-08-30 | Hitachi, Ltd. | Recrystallized CMOS with different crystal planes |
JPS6292361A (ja) * | 1985-10-17 | 1987-04-27 | Toshiba Corp | 相補型半導体装置 |
JPS63228662A (ja) * | 1987-03-18 | 1988-09-22 | Toshiba Corp | 相補型mos半導体装置の製造方法 |
JP2685819B2 (ja) * | 1988-03-31 | 1997-12-03 | 株式会社東芝 | 誘電体分離半導体基板とその製造方法 |
-
1991
- 1991-10-01 JP JP3253899A patent/JP3017860B2/ja not_active Expired - Lifetime
-
1992
- 1992-09-29 KR KR92017763A patent/KR960008733B1/ko not_active IP Right Cessation
- 1992-09-30 US US07/953,808 patent/US5384473A/en not_active Expired - Lifetime
- 1992-10-01 DE DE69230458T patent/DE69230458T2/de not_active Expired - Lifetime
- 1992-10-01 EP EP92116847A patent/EP0535681B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP3017860B2 (ja) | 2000-03-13 |
US5384473A (en) | 1995-01-24 |
EP0535681A3 (en) | 1996-01-17 |
EP0535681A2 (de) | 1993-04-07 |
JPH0594928A (ja) | 1993-04-16 |
KR930009103A (ko) | 1993-05-22 |
DE69230458D1 (de) | 2000-01-27 |
KR960008733B1 (en) | 1996-06-29 |
EP0535681B1 (de) | 1999-12-22 |
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