DE69231028D1 - Serieller zugriffspeicher - Google Patents

Serieller zugriffspeicher

Info

Publication number
DE69231028D1
DE69231028D1 DE69231028T DE69231028T DE69231028D1 DE 69231028 D1 DE69231028 D1 DE 69231028D1 DE 69231028 T DE69231028 T DE 69231028T DE 69231028 T DE69231028 T DE 69231028T DE 69231028 D1 DE69231028 D1 DE 69231028D1
Authority
DE
Germany
Prior art keywords
access storage
serial access
serial
storage
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69231028T
Other languages
English (en)
Other versions
DE69231028T2 (de
Inventor
Atsushi Takasugi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69231028D1 publication Critical patent/DE69231028D1/de
Publication of DE69231028T2 publication Critical patent/DE69231028T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69231028T 1991-06-04 1992-06-03 Serieller zugriffspeicher Expired - Fee Related DE69231028T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP13307491 1991-06-04
PCT/JP1992/000717 WO1992022068A1 (en) 1991-06-04 1992-06-03 Serial access memory

Publications (2)

Publication Number Publication Date
DE69231028D1 true DE69231028D1 (de) 2000-06-15
DE69231028T2 DE69231028T2 (de) 2001-02-15

Family

ID=15096241

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231028T Expired - Fee Related DE69231028T2 (de) 1991-06-04 1992-06-03 Serieller zugriffspeicher

Country Status (6)

Country Link
US (1) US5369618A (de)
EP (1) EP0544012B1 (de)
JP (1) JP3370092B2 (de)
KR (1) KR100257595B1 (de)
DE (1) DE69231028T2 (de)
WO (1) WO1992022068A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581773A (en) * 1992-05-12 1996-12-03 Glover; Michael A. Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements
JP3406790B2 (ja) * 1996-11-25 2003-05-12 株式会社東芝 データ転送システム及びデータ転送方法
KR100305647B1 (ko) * 1998-05-27 2002-03-08 박종섭 동기식메모리장치
US6557051B1 (en) * 2000-01-15 2003-04-29 Cirrus Logic, Inc. Throughput for a serial interface
US6985388B2 (en) 2001-09-17 2006-01-10 Sandisk Corporation Dynamic column block selection
JP5133734B2 (ja) * 2008-02-26 2013-01-30 セイコーインスツル株式会社 イメージセンサ
JP2010182377A (ja) * 2009-02-05 2010-08-19 Toshiba Corp 半導体記憶装置
US7974124B2 (en) 2009-06-24 2011-07-05 Sandisk Corporation Pointer based column selection techniques in non-volatile memories
JP5314612B2 (ja) 2010-02-04 2013-10-16 ルネサスエレクトロニクス株式会社 半導体記憶装置
US8842473B2 (en) 2012-03-15 2014-09-23 Sandisk Technologies Inc. Techniques for accessing column selecting shift register with skipped entries in non-volatile memories
CN107479681A (zh) * 2017-09-19 2017-12-15 联想(北京)有限公司 数字电源及其系统和实现方法、以及数字电源组

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868284A (ja) * 1981-10-19 1983-04-23 Nippon Telegr & Teleph Corp <Ntt> 集積記憶回路
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
US5170157A (en) * 1986-05-20 1992-12-08 Takatoshi Ishii Memory device for an image display apparatus having a serial port and independently operable data registers
JPS62271291A (ja) * 1986-05-20 1987-11-25 Ascii Corp メモリ装置
JPS63225990A (ja) * 1987-03-16 1988-09-20 Hitachi Ltd 半導体記憶装置
JPS63268188A (ja) * 1987-04-24 1988-11-04 Nec Corp Ｄｒａｍのアクセス制御回路
US5193071A (en) * 1988-12-22 1993-03-09 Digital Equipment Corporation Memory apparatus for multiple processor systems
JP3035956B2 (ja) * 1989-02-27 2000-04-24 日本電気株式会社 書込みマスク可能な半導体メモリ装置
JPH03237684A (ja) * 1990-02-14 1991-10-23 Fujitsu Ltd 画像記憶装置
JPH0479422A (ja) * 1990-07-18 1992-03-12 Nec Corp 送信制御回路
JPH04298882A (ja) * 1991-03-28 1992-10-22 Nec Corp デュアルポートメモリ

Also Published As

Publication number Publication date
EP0544012B1 (de) 2000-05-10
KR930701814A (ko) 1993-06-12
EP0544012A1 (de) 1993-06-02
US5369618A (en) 1994-11-29
KR100257595B1 (ko) 2000-06-01
WO1992022068A1 (en) 1992-12-10
DE69231028T2 (de) 2001-02-15
JP3370092B2 (ja) 2003-01-27
EP0544012A4 (en) 1998-07-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP

8339 Ceased/non-payment of the annual fee