DE69231497D1 - Massivparalleles rechnersystem mit eingangs-ausgangsanordnung - Google Patents
Massivparalleles rechnersystem mit eingangs-ausgangsanordnungInfo
- Publication number
- DE69231497D1 DE69231497D1 DE69231497T DE69231497T DE69231497D1 DE 69231497 D1 DE69231497 D1 DE 69231497D1 DE 69231497 T DE69231497 T DE 69231497T DE 69231497 T DE69231497 T DE 69231497T DE 69231497 D1 DE69231497 D1 DE 69231497D1
- Authority
- DE
- Germany
- Prior art keywords
- input
- computer system
- massively parallel
- parallel computer
- output arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
- G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/555—Error detection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/88—Monitoring involving counting
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/746,038 US5361363A (en) | 1990-10-03 | 1991-08-16 | Input/output system for parallel computer for performing parallel file transfers between selected number of input/output devices and another selected number of processing nodes |
PCT/US1992/006848 WO1993004438A1 (en) | 1991-08-16 | 1992-08-13 | Input/output arrangement for massively parallel computer system |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69231497D1 true DE69231497D1 (de) | 2000-11-09 |
DE69231497T2 DE69231497T2 (de) | 2001-02-08 |
Family
ID=24999241
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69231497T Expired - Fee Related DE69231497T2 (de) | 1991-08-16 | 1992-08-13 | Massivparalleles rechnersystem mit eingangs-ausgangsanordnung |
Country Status (7)
Country | Link |
---|---|
US (1) | US5361363A (de) |
EP (1) | EP0601029B1 (de) |
JP (1) | JPH06509894A (de) |
AU (1) | AU674832B2 (de) |
CA (1) | CA2115738A1 (de) |
DE (1) | DE69231497T2 (de) |
WO (1) | WO1993004438A1 (de) |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2770603B2 (ja) * | 1991-03-14 | 1998-07-02 | 三菱電機株式会社 | 並列計算機 |
JPH06208460A (ja) * | 1993-01-11 | 1994-07-26 | Hitachi Ltd | マイクロプログラムメモリ制御方式 |
US5987622A (en) * | 1993-12-10 | 1999-11-16 | Tm Patents, Lp | Parallel computer system including parallel storage subsystem including facility for correction of data in the event of failure of a storage device in parallel storage subsystem |
US5590356A (en) * | 1994-08-23 | 1996-12-31 | Massachusetts Institute Of Technology | Mesh parallel computer architecture apparatus and associated methods |
US5781551A (en) * | 1994-09-15 | 1998-07-14 | Texas Instruments Incorporated | Computer communications system with tree architecture and communications method |
US5587997A (en) * | 1995-02-24 | 1996-12-24 | Hewlett-Packard Company | Method and apparatus for determining when all packets of a message have arrived |
US5745915A (en) * | 1995-03-17 | 1998-04-28 | Unisys Corporation | System for parallel reading and processing of a file |
DE19626287A1 (de) * | 1996-07-01 | 1997-02-13 | Abb Management Ag | Verfahren zum Betrieb eines Antriebssystems und Vorrichtung zur Durchführung des Verfahrens |
JPH10124366A (ja) * | 1996-10-18 | 1998-05-15 | Nec Corp | ファイルデータ格納機構の並列管理方式 |
US5915088A (en) * | 1996-12-05 | 1999-06-22 | Tandem Computers Incorporated | Interprocessor messaging system |
KR100207598B1 (ko) * | 1997-01-27 | 1999-07-15 | 윤종용 | 상호연결망으로서 파이브 채널을 사용한 클러스터시스템 |
US6266732B1 (en) * | 1998-05-29 | 2001-07-24 | 3Com Corporation | Interrupt events chaining |
US6119215A (en) | 1998-06-29 | 2000-09-12 | Cisco Technology, Inc. | Synchronization and control system for an arrayed processing engine |
US6356548B1 (en) | 1998-06-29 | 2002-03-12 | Cisco Technology, Inc. | Pooled receive and transmit queues to access a shared bus in a multi-port switch asic |
US6195739B1 (en) | 1998-06-29 | 2001-02-27 | Cisco Technology, Inc. | Method and apparatus for passing data among processor complex stages of a pipelined processing engine |
US6101599A (en) * | 1998-06-29 | 2000-08-08 | Cisco Technology, Inc. | System for context switching between processing elements in a pipeline of processing elements |
US6836838B1 (en) | 1998-06-29 | 2004-12-28 | Cisco Technology, Inc. | Architecture for a processor complex of an arrayed pipelined processing engine |
US6513108B1 (en) | 1998-06-29 | 2003-01-28 | Cisco Technology, Inc. | Programmable processing engine for efficiently processing transient data |
US6728839B1 (en) | 1998-10-28 | 2004-04-27 | Cisco Technology, Inc. | Attribute based memory pre-fetching technique |
US6385747B1 (en) | 1998-12-14 | 2002-05-07 | Cisco Technology, Inc. | Testing of replicated components of electronic device |
US6173386B1 (en) | 1998-12-14 | 2001-01-09 | Cisco Technology, Inc. | Parallel processor with debug capability |
US6920562B1 (en) | 1998-12-18 | 2005-07-19 | Cisco Technology, Inc. | Tightly coupled software protocol decode with hardware data encryption |
US6618371B1 (en) * | 1999-06-08 | 2003-09-09 | Cisco Technology, Inc. | Butterfly network with switches set for two node disjoint paths and method for forming the paths |
US6681341B1 (en) | 1999-11-03 | 2004-01-20 | Cisco Technology, Inc. | Processor isolation method for integrated multi-processor systems |
US6529983B1 (en) | 1999-11-03 | 2003-03-04 | Cisco Technology, Inc. | Group and virtual locking mechanism for inter processor synchronization |
US8160863B2 (en) * | 2000-03-28 | 2012-04-17 | Ionipas Transfer Company, Llc | System and method for connecting a logic circuit simulation to a network |
US6892237B1 (en) | 2000-03-28 | 2005-05-10 | Cisco Technology, Inc. | Method and apparatus for high-speed parsing of network messages |
US7266490B2 (en) * | 2000-12-28 | 2007-09-04 | Robert Marc Zeidman | Apparatus and method for connecting hardware to a circuit simulation |
AU2000241369A1 (en) * | 2000-04-20 | 2001-11-07 | Nokia Corporation | A communication terminal |
US6505269B1 (en) | 2000-05-16 | 2003-01-07 | Cisco Technology, Inc. | Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system |
US6967950B2 (en) * | 2000-08-11 | 2005-11-22 | Texas Instruments Incorporated | Pull transfers and transfer receipt confirmation in a datapipe routing bridge |
US6732253B1 (en) | 2000-11-13 | 2004-05-04 | Chipwrights Design, Inc. | Loop handling for single instruction multiple datapath processor architectures |
US6931518B1 (en) | 2000-11-28 | 2005-08-16 | Chipwrights Design, Inc. | Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic |
US20070016396A9 (en) * | 2000-12-28 | 2007-01-18 | Zeidman Robert M | Apparatus and method for connecting a hardware emulator to a computer peripheral |
US7302548B1 (en) | 2002-06-18 | 2007-11-27 | Cisco Technology, Inc. | System and method for communicating in a multi-processor environment |
US6970985B2 (en) | 2002-07-09 | 2005-11-29 | Bluerisc Inc. | Statically speculative memory accessing |
US20060001669A1 (en) * | 2002-12-02 | 2006-01-05 | Sehat Sutardja | Self-reparable semiconductor and method thereof |
US20050114850A1 (en) | 2003-10-29 | 2005-05-26 | Saurabh Chheda | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
US7996671B2 (en) | 2003-11-17 | 2011-08-09 | Bluerisc Inc. | Security of program executables and microprocessors based on compiler-architecture interaction |
US8607209B2 (en) | 2004-02-04 | 2013-12-10 | Bluerisc Inc. | Energy-focused compiler-assisted branch prediction |
DE602004008346T2 (de) * | 2004-02-16 | 2008-05-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Adressmanagement in auf mobilem ip basierten umgebungen |
JP3835459B2 (ja) * | 2004-03-09 | 2006-10-18 | セイコーエプソン株式会社 | データ転送制御装置及び電子機器 |
US20070083574A1 (en) * | 2005-10-07 | 2007-04-12 | Oracle International Corporation | Replica database maintenance with parallel log file transfers |
CN100563203C (zh) * | 2005-11-11 | 2009-11-25 | 华为技术有限公司 | 通信网络中组播树叶子节点网元信号传送的方法 |
US20080126766A1 (en) | 2006-11-03 | 2008-05-29 | Saurabh Chheda | Securing microprocessors against information leakage and physical tampering |
JP4913685B2 (ja) * | 2007-07-04 | 2012-04-11 | 株式会社リコー | Simd型マイクロプロセッサおよびsimd型マイクロプロセッサの制御方法 |
JP2009301101A (ja) * | 2008-06-10 | 2009-12-24 | Nec Corp | プロセッサ間通信システム、プロセッサ、プロセッサ間通信方法、および、通信方法 |
US8755515B1 (en) | 2008-09-29 | 2014-06-17 | Wai Wu | Parallel signal processing system and method |
DE102009021136A1 (de) * | 2009-05-13 | 2010-12-16 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Regelvorrichtung |
JP5347772B2 (ja) * | 2009-07-01 | 2013-11-20 | 富士通株式会社 | 転送速度設定方法、データ転送装置及び情報処理システム |
US8571834B2 (en) * | 2010-01-08 | 2013-10-29 | International Business Machines Corporation | Opcode counting for performance measurement |
JP5501052B2 (ja) * | 2010-03-24 | 2014-05-21 | キヤノン株式会社 | 通信装置、通信装置の制御方法、プログラム |
US8589867B2 (en) | 2010-06-18 | 2013-11-19 | Microsoft Corporation | Compiler-generated invocation stubs for data parallel programming model |
US20110314256A1 (en) * | 2010-06-18 | 2011-12-22 | Microsoft Corporation | Data Parallel Programming Model |
WO2012101833A1 (ja) * | 2011-01-30 | 2012-08-02 | 富士通株式会社 | 演算装置および演算方法 |
JP6673202B2 (ja) * | 2014-06-19 | 2020-03-25 | 日本電気株式会社 | 演算装置、演算装置の制御方法、及び、演算装置の制御プログラム |
US11502934B2 (en) * | 2018-08-21 | 2022-11-15 | The George Washington Univesity | EZ-pass: an energy performance-efficient power-gating router architecture for scalable on-chip interconnect architecture |
US11314674B2 (en) * | 2020-02-14 | 2022-04-26 | Google Llc | Direct memory access architecture with multi-level multi-striding |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0097351A3 (de) * | 1982-06-21 | 1986-02-26 | Nec Corporation | Wegesucheinheit und Wegesuchnetz zur Bestimmung eines Ausgangsports durch Erkennung eines Teiles eines Eingangspakets |
US4598400A (en) * | 1983-05-31 | 1986-07-01 | Thinking Machines Corporation | Method and apparatus for routing message packets |
US4873626A (en) * | 1986-12-17 | 1989-10-10 | Massachusetts Institute Of Technology | Parallel processing system with processor array having memory system included in system memory |
US4910669A (en) * | 1987-04-03 | 1990-03-20 | At&T Bell Laboratories | Binary tree multiprocessor |
US5111389A (en) * | 1987-10-29 | 1992-05-05 | International Business Machines Corporation | Aperiodic mapping system using power-of-two stride access to interleaved devices |
-
1991
- 1991-08-16 US US07/746,038 patent/US5361363A/en not_active Expired - Lifetime
-
1992
- 1992-08-13 CA CA002115738A patent/CA2115738A1/en not_active Abandoned
- 1992-08-13 EP EP92918507A patent/EP0601029B1/de not_active Expired - Lifetime
- 1992-08-13 JP JP5504468A patent/JPH06509894A/ja active Pending
- 1992-08-13 AU AU24868/92A patent/AU674832B2/en not_active Ceased
- 1992-08-13 WO PCT/US1992/006848 patent/WO1993004438A1/en active IP Right Grant
- 1992-08-13 DE DE69231497T patent/DE69231497T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5361363A (en) | 1994-11-01 |
EP0601029A4 (de) | 1995-02-22 |
AU674832B2 (en) | 1997-01-16 |
DE69231497T2 (de) | 2001-02-08 |
WO1993004438A1 (en) | 1993-03-04 |
AU2486892A (en) | 1993-03-16 |
JPH06509894A (ja) | 1994-11-02 |
EP0601029B1 (de) | 2000-10-04 |
CA2115738A1 (en) | 1993-03-04 |
EP0601029A1 (de) | 1994-06-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |