DE69232880T2 - Bittaktrückgewinnungsschaltung - Google Patents
BittaktrückgewinnungsschaltungInfo
- Publication number
- DE69232880T2 DE69232880T2 DE69232880T DE69232880T DE69232880T2 DE 69232880 T2 DE69232880 T2 DE 69232880T2 DE 69232880 T DE69232880 T DE 69232880T DE 69232880 T DE69232880 T DE 69232880T DE 69232880 T2 DE69232880 T2 DE 69232880T2
- Authority
- DE
- Germany
- Prior art keywords
- bittaktrückgewinnungsschaltung
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3074777A JPH04286248A (ja) | 1991-03-14 | 1991-03-14 | ベースバンド遅延検波器 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69232880D1 DE69232880D1 (de) | 2003-02-06 |
DE69232880T2 true DE69232880T2 (de) | 2003-08-28 |
Family
ID=13557063
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69232880T Expired - Fee Related DE69232880T2 (de) | 1991-03-14 | 1992-03-12 | Bittaktrückgewinnungsschaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US5317602A (de) |
EP (1) | EP0503632B1 (de) |
JP (1) | JPH04286248A (de) |
DE (1) | DE69232880T2 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2319915B (en) * | 1996-11-29 | 2001-01-24 | Lsi Logic Corp | Analogue to digital converter system |
US5550869A (en) * | 1992-12-30 | 1996-08-27 | Comstream Corporation | Demodulator for consumer uses |
JPH0746217A (ja) * | 1993-07-26 | 1995-02-14 | Sony Corp | ディジタル復調装置 |
JP3403849B2 (ja) * | 1995-03-17 | 2003-05-06 | 富士通株式会社 | 多重無線装置の受信部に設けられるクロック位相検出回路及びクロック再生回路 |
JP3484980B2 (ja) | 1998-06-23 | 2004-01-06 | 日本電気株式会社 | 無線受信機 |
US6363129B1 (en) * | 1998-11-09 | 2002-03-26 | Broadcom Corporation | Timing recovery system for a multi-pair gigabit transceiver |
FR2793570A1 (fr) * | 1999-05-11 | 2000-11-17 | Koninkl Philips Electronics Nv | Processeur ayant une frequence de fonctionnement adaptable |
US6127884A (en) * | 1999-05-24 | 2000-10-03 | Philips Electronics North America Corp. | Differentiate and multiply based timing recovery in a quadrature demodulator |
US7450944B2 (en) * | 2005-11-03 | 2008-11-11 | Motorola, Inc. | Method and apparatus for base station synchronization |
CN100578378C (zh) * | 2006-01-25 | 2010-01-06 | 株式会社理光 | 图像形成装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3993956A (en) * | 1975-11-03 | 1976-11-23 | Motorola, Inc. | Digital detection system for differential phase shift keyed signals |
GB2110020A (en) * | 1981-11-09 | 1983-06-08 | Philips Electronic Associated | Deriving a clock signal from a received digital signal |
US4535459A (en) * | 1983-05-26 | 1985-08-13 | Rockwell International Corporation | Signal detection apparatus |
FR2628916B1 (fr) * | 1988-03-15 | 1990-06-29 | Alcatel Thomson Faisceaux | Dispositif de synchronisation en modulation de phase a quatre etats decalee |
JPH0716206B2 (ja) * | 1988-08-05 | 1995-02-22 | 日本電気株式会社 | 信号検出器 |
KR920003598B1 (ko) * | 1988-12-22 | 1992-05-04 | 재단법인 한국전자통신 연구소 | Nrz비트 동기방식의 주파수 및 위상검출회로 |
US5175544A (en) * | 1990-04-27 | 1992-12-29 | Veda Systems Incorporated | Digitally controlled bit synchronizer |
-
1991
- 1991-03-14 JP JP3074777A patent/JPH04286248A/ja not_active Withdrawn
-
1992
- 1992-03-12 EP EP92104295A patent/EP0503632B1/de not_active Expired - Lifetime
- 1992-03-12 DE DE69232880T patent/DE69232880T2/de not_active Expired - Fee Related
- 1992-03-13 US US07/851,559 patent/US5317602A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH04286248A (ja) | 1992-10-12 |
EP0503632B1 (de) | 2003-01-02 |
EP0503632A3 (en) | 1993-03-17 |
EP0503632A2 (de) | 1992-09-16 |
DE69232880D1 (de) | 2003-02-06 |
US5317602A (en) | 1994-05-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |