DE69302960T2 - Verfahren zur Herstellung von dünnen Siliziummesas mit gleicher Dicke - Google Patents

Verfahren zur Herstellung von dünnen Siliziummesas mit gleicher Dicke

Info

Publication number
DE69302960T2
DE69302960T2 DE69302960T DE69302960T DE69302960T2 DE 69302960 T2 DE69302960 T2 DE 69302960T2 DE 69302960 T DE69302960 T DE 69302960T DE 69302960 T DE69302960 T DE 69302960T DE 69302960 T2 DE69302960 T2 DE 69302960T2
Authority
DE
Germany
Prior art keywords
production
same thickness
thin silicon
silicon mesas
mesas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69302960T
Other languages
English (en)
Other versions
DE69302960D1 (de
Inventor
George William Doerre
Seiki Ogura
Nivo Rovedo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69302960D1 publication Critical patent/DE69302960D1/de
Publication of DE69302960T2 publication Critical patent/DE69302960T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material
DE69302960T 1992-04-30 1993-03-23 Verfahren zur Herstellung von dünnen Siliziummesas mit gleicher Dicke Expired - Fee Related DE69302960T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/876,598 US5334281A (en) 1992-04-30 1992-04-30 Method of forming thin silicon mesas having uniform thickness

Publications (2)

Publication Number Publication Date
DE69302960D1 DE69302960D1 (de) 1996-07-11
DE69302960T2 true DE69302960T2 (de) 1996-12-12

Family

ID=25368105

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69302960T Expired - Fee Related DE69302960T2 (de) 1992-04-30 1993-03-23 Verfahren zur Herstellung von dünnen Siliziummesas mit gleicher Dicke

Country Status (4)

Country Link
US (1) US5334281A (de)
EP (1) EP0568475B1 (de)
JP (1) JP2579418B2 (de)
DE (1) DE69302960T2 (de)

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JP2818790B2 (ja) * 1989-11-28 1998-10-30 出光石油化学株式会社 軟質ポリプロピレン系複合材料
JP3060714B2 (ja) * 1992-04-15 2000-07-10 日本電気株式会社 半導体集積回路の製造方法
US5264387A (en) * 1992-10-27 1993-11-23 International Business Machines Corporation Method of forming uniformly thin, isolated silicon mesas on an insulating substrate
US5439551A (en) * 1994-03-02 1995-08-08 Micron Technology, Inc. Chemical-mechanical polishing techniques and methods of end point detection in chemical-mechanical polishing processes
US5482871A (en) * 1994-04-15 1996-01-09 Texas Instruments Incorporated Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate
US6069081A (en) * 1995-04-28 2000-05-30 International Buiness Machines Corporation Two-step chemical mechanical polish surface planarization technique
JP3008858B2 (ja) * 1996-09-06 2000-02-14 日本電気株式会社 半導体装置の製造方法
US5882982A (en) * 1997-01-16 1999-03-16 Vlsi Technology, Inc. Trench isolation method
US6025244A (en) * 1997-12-04 2000-02-15 Fujitsu Limited Self-aligned patterns by chemical-mechanical polishing particularly suited to the formation of MCM capacitors
US5994229A (en) * 1998-01-12 1999-11-30 Taiwan Semiconductor Manufacturing Company Ltd. Achievement of top rounding in shallow trench etch
US6863593B1 (en) 1998-11-02 2005-03-08 Applied Materials, Inc. Chemical mechanical polishing a substrate having a filler layer and a stop layer
US6818952B2 (en) * 2002-10-01 2004-11-16 International Business Machines Corporation Damascene gate multi-mesa MOSFET
IL155554A0 (en) * 2003-04-24 2003-11-23 J G Systems Inc Chemical-mechanical polishing composition and process
US7235440B2 (en) * 2003-07-31 2007-06-26 Tokyo Electron Limited Formation of ultra-thin oxide layers by self-limiting interfacial oxidation
US7202186B2 (en) * 2003-07-31 2007-04-10 Tokyo Electron Limited Method of forming uniform ultra-thin oxynitride layers
US7202123B1 (en) 2004-07-02 2007-04-10 Advanced Micro Devices, Inc. Mesa isolation technology for extremely thin silicon-on-insulator semiconductor devices
EP2174122A2 (de) * 2007-06-08 2010-04-14 Bharath R Takulapalli Nanostrukturierter feldeffektsensor sowie verfahren zu seiner herstellung und verwendung
US8288280B2 (en) * 2007-07-19 2012-10-16 Macronix International Co., Ltd. Conductor removal process
EP2836828B1 (de) 2012-04-09 2022-12-14 Takulapalli, Bharath Feldeffekttransistor, vorrichtung mit diesem transistor und verfahren zur herstellung und verwendung davon

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1186340A (en) * 1968-07-11 1970-04-02 Standard Telephones Cables Ltd Manufacture of Semiconductor Devices
US3929528A (en) * 1973-01-12 1975-12-30 Motorola Inc Fabrication of monocriptalline silicon on insulating substrates utilizing selective etching and deposition techniques
NL7710164A (nl) * 1977-09-16 1979-03-20 Philips Nv Werkwijze ter behandeling van een eenkristal- lijn lichaam.
IT7826422A0 (it) * 1977-09-22 1978-08-02 Rca Corp Circuito integrato planare a silicio su zaffiro (sos) e metodo per la fabbricazione dello stesso.
US4554059A (en) * 1983-11-04 1985-11-19 Harris Corporation Electrochemical dielectric isolation technique
JPS61120424A (ja) * 1984-11-16 1986-06-07 Oki Electric Ind Co Ltd 誘電体分離基板の研磨方法
JPS6298639A (ja) * 1985-10-24 1987-05-08 Nec Corp 誘電体分離基板の製造方法
NL8700033A (nl) * 1987-01-09 1988-08-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting van het type halfgeleider op isolator.
US4735679A (en) * 1987-03-30 1988-04-05 International Business Machines Corporation Method of improving silicon-on-insulator uniformity
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding
US4902641A (en) * 1987-07-31 1990-02-20 Motorola, Inc. Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure
US4897362A (en) * 1987-09-02 1990-01-30 Harris Corporation Double epitaxial method of fabricating semiconductor devices on bonded wafers
JPH067594B2 (ja) * 1987-11-20 1994-01-26 富士通株式会社 半導体基板の製造方法
NL8801981A (nl) * 1988-08-09 1990-03-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
DE68927871T2 (de) * 1988-11-09 1997-07-03 Sony Corp Herstellungsverfahren eines Halbleiterwafers
JPH02219266A (ja) * 1989-02-20 1990-08-31 Toshiba Corp Ｓｏｉ積層半導体基板の製造方法
EP0391081A3 (de) * 1989-04-06 1991-08-07 International Business Machines Corporation Herstellung und Struktur von Halbleiter auf Isolatorinseln
JPH0636414B2 (ja) * 1989-08-17 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
JP2803295B2 (ja) * 1990-02-28 1998-09-24 富士通株式会社 Ｓｏｉ基板と半導体装置及びその製造方法
US5034343A (en) * 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
JPH03270254A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH0621206A (ja) 1994-01-28
US5334281A (en) 1994-08-02
EP0568475A1 (de) 1993-11-03
DE69302960D1 (de) 1996-07-11
JP2579418B2 (ja) 1997-02-05
EP0568475B1 (de) 1996-06-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee