DE69314679D1 - Mit schwerschmelzendem Metal abgedeckte metallische Leiterbahnen und Kontaktlöcher - Google Patents

Mit schwerschmelzendem Metal abgedeckte metallische Leiterbahnen und Kontaktlöcher

Info

Publication number
DE69314679D1
DE69314679D1 DE69314679T DE69314679T DE69314679D1 DE 69314679 D1 DE69314679 D1 DE 69314679D1 DE 69314679 T DE69314679 T DE 69314679T DE 69314679 T DE69314679 T DE 69314679T DE 69314679 D1 DE69314679 D1 DE 69314679D1
Authority
DE
Germany
Prior art keywords
trench
hole
metallization
metal
low resistivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69314679T
Other languages
English (en)
Other versions
DE69314679T2 (de
Inventor
William Joseph Cote
Pei-Ing Paul Lee
Thomas Edwin Sandwick
Bernd Michael Vollmer
Victor Vynorius
Stuart Howard Wolff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
Siemens AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, International Business Machines Corp filed Critical Siemens AG
Publication of DE69314679D1 publication Critical patent/DE69314679D1/de
Application granted granted Critical
Publication of DE69314679T2 publication Critical patent/DE69314679T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
DE69314679T 1992-02-26 1993-02-25 Mit schwerschmelzendem Metal abgedeckte metallische Leiterbahnen und Kontaktlöcher Expired - Fee Related DE69314679T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/841,693 US5262354A (en) 1992-02-26 1992-02-26 Refractory metal capped low resistivity metal conductor lines and vias

Publications (2)

Publication Number Publication Date
DE69314679D1 true DE69314679D1 (de) 1997-11-27
DE69314679T2 DE69314679T2 (de) 1998-04-02

Family

ID=25285485

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69314679T Expired - Fee Related DE69314679T2 (de) 1992-02-26 1993-02-25 Mit schwerschmelzendem Metal abgedeckte metallische Leiterbahnen und Kontaktlöcher

Country Status (9)

Country Link
US (1) US5262354A (de)
EP (1) EP0558004B1 (de)
JP (1) JP2989408B2 (de)
KR (1) KR970006973B1 (de)
CN (1) CN1027610C (de)
AT (1) ATE159615T1 (de)
DE (1) DE69314679T2 (de)
HK (1) HK1001601A1 (de)
TW (1) TW367599B (de)

Families Citing this family (133)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
DE59308407D1 (de) * 1993-01-19 1998-05-20 Siemens Ag Verfahren zur Herstellung einer Kontakte und diese verbindende Leiterbahnen umfassenden Metallisierungsebene
KR960004095B1 (en) * 1993-02-17 1996-03-26 Hyundai Electronics Ind Manufacturing method of metal plug in contact-hole
JP3326698B2 (ja) * 1993-03-19 2002-09-24 富士通株式会社 集積回路装置の製造方法
JP3360350B2 (ja) * 1993-04-21 2002-12-24 ヤマハ株式会社 表面平坦化法
JP2699839B2 (ja) * 1993-12-03 1998-01-19 日本電気株式会社 半導体装置の製造方法
US5642073A (en) 1993-12-06 1997-06-24 Micron Technology, Inc. System powered with inter-coupled charge pumps
KR0124644B1 (ko) * 1994-05-10 1997-12-11 문정환 반도체소자의 다층금속배선의 형성방법
US5447874A (en) * 1994-07-29 1995-09-05 Grivna; Gordon Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish
EP0915501B1 (de) * 1994-08-05 2003-02-26 International Business Machines Corporation Verfahren zur Herstellung einer Damaszenstruktur mit einer WGe Polierstoppschicht
US5686356A (en) 1994-09-30 1997-11-11 Texas Instruments Incorporated Conductor reticulation for improved device planarity
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5529953A (en) * 1994-10-14 1996-06-25 Toshiba America Electronic Components, Inc. Method of forming studs and interconnects in a multi-layered semiconductor device
US5602423A (en) * 1994-11-01 1997-02-11 Texas Instruments Incorporated Damascene conductors with embedded pillars
KR960026249A (ko) * 1994-12-12 1996-07-22 윌리엄 이. 힐러 고압, 저온 반도체 갭 충진 프로세스
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
TW290731B (de) * 1995-03-30 1996-11-11 Siemens Ag
KR0179827B1 (ko) * 1995-05-27 1999-04-15 문정환 반도체 소자의 배선 형성방법
WO1996038859A1 (en) * 1995-06-02 1996-12-05 Advanced Micro Devices, Inc. Surface conditioning insulating layer for fine line conductive pattern
US5665201A (en) * 1995-06-06 1997-09-09 Advanced Micro Devices, Inc. High removal rate chemical-mechanical polishing
US5686354A (en) * 1995-06-07 1997-11-11 Advanced Micro Devices, Inc. Dual damascene with a protective mask for via etching
US5691238A (en) * 1995-06-07 1997-11-25 Advanced Micro Devices, Inc. Subtractive dual damascene
US5702563A (en) * 1995-06-07 1997-12-30 Advanced Micro Devices, Inc. Reduced chemical-mechanical polishing particulate contamination
US5614765A (en) * 1995-06-07 1997-03-25 Advanced Micro Devices, Inc. Self aligned via dual damascene
US5705430A (en) * 1995-06-07 1998-01-06 Advanced Micro Devices, Inc. Dual damascene with a sacrificial via fill
US5712510A (en) * 1995-08-04 1998-01-27 Advanced Micro Devices, Inc. Reduced electromigration interconnection line
JP3274324B2 (ja) * 1995-09-01 2002-04-15 株式会社東芝 半導体装置の製造方法
US5689139A (en) * 1995-09-11 1997-11-18 Advanced Micro Devices, Inc. Enhanced electromigration lifetime of metal interconnection lines
JPH10509285A (ja) * 1995-09-14 1998-09-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 縮小したフィーチャーサイズのためのダマスクプロセス
US6743723B2 (en) 1995-09-14 2004-06-01 Canon Kabushiki Kaisha Method for fabricating semiconductor device
US5693568A (en) * 1995-12-14 1997-12-02 Advanced Micro Devices, Inc. Reverse damascene via structures
US5858832A (en) * 1996-03-11 1999-01-12 Chartered Semiconduction Manufacturing Ltd. Method for forming a high areal capacitance planar capacitor
US5976970A (en) * 1996-03-29 1999-11-02 International Business Machines Corporation Method of making and laterally filling key hole structure for ultra fine pitch conductor lines
US5654216A (en) * 1996-04-08 1997-08-05 Chartered Semiconductor Manufacturing Pte Ltd. Formation of a metal via structure from a composite metal layer
JP3304754B2 (ja) 1996-04-11 2002-07-22 三菱電機株式会社 集積回路の多段埋め込み配線構造
US5843839A (en) * 1996-04-29 1998-12-01 Chartered Semiconductor Manufacturing, Ltd. Formation of a metal via using a raised metal plug structure
US5814557A (en) * 1996-05-20 1998-09-29 Motorola, Inc. Method of forming an interconnect structure
US5948700A (en) * 1996-05-20 1999-09-07 Chartered Semiconductor Manufacturing Ltd. Method of planarization of an intermetal dielectric layer using chemical mechanical polishing
US5801093A (en) * 1996-06-13 1998-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Process for creating vias using pillar technology
US5663108A (en) * 1996-06-13 1997-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Optimized metal pillar via process
US6077768A (en) * 1996-07-19 2000-06-20 Motorola, Inc. Process for fabricating a multilevel interconnect
US6309971B1 (en) 1996-08-01 2001-10-30 Cypress Semiconductor Corporation Hot metallization process
US5956612A (en) * 1996-08-09 1999-09-21 Micron Technology, Inc. Trench/hole fill processes for semiconductor fabrication
US5972792A (en) * 1996-10-18 1999-10-26 Micron Technology, Inc. Method for chemical-mechanical planarization of a substrate on a fixed-abrasive polishing pad
US5861676A (en) * 1996-11-27 1999-01-19 Cypress Semiconductor Corp. Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit
US6110396A (en) 1996-11-27 2000-08-29 International Business Machines Corporation Dual-valent rare earth additives to polishing slurries
US5876490A (en) * 1996-12-09 1999-03-02 International Business Machines Corporatin Polish process and slurry for planarization
US5897371A (en) * 1996-12-19 1999-04-27 Cypress Semiconductor Corp. Alignment process compatible with chemical mechanical polishing
US6537905B1 (en) 1996-12-30 2003-03-25 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
JPH10209279A (ja) * 1997-01-27 1998-08-07 Matsushita Electron Corp 金属プラグの形成方法
US5780204A (en) * 1997-02-03 1998-07-14 Advanced Micro Devices, Inc. Backside wafer polishing for improved photolithography
US5863707A (en) * 1997-02-11 1999-01-26 Advanced Micro Devices, Inc. Method for producing ultra-fine interconnection features
US6136510A (en) * 1997-02-13 2000-10-24 Advanced Micro Devices, Inc. Doubled-sided wafer scrubbing for improved photolithography
JP3228181B2 (ja) 1997-05-12 2001-11-12 ヤマハ株式会社 平坦配線形成法
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US5833820A (en) * 1997-06-19 1998-11-10 Advanced Micro Devices, Inc. Electroplating apparatus
US5899706A (en) * 1997-06-30 1999-05-04 Siemens Aktiengesellschaft Method of reducing loading variation during etch processing
US5972192A (en) * 1997-07-23 1999-10-26 Advanced Micro Devices, Inc. Pulse electroplating copper or copper alloys
US6240199B1 (en) 1997-07-24 2001-05-29 Agere Systems Guardian Corp. Electronic apparatus having improved scratch and mechanical resistance
US6175145B1 (en) * 1997-07-26 2001-01-16 Samsung Electronics Co., Ltd. Method of making a fuse in a semiconductor device and a semiconductor device having a fuse
US5989623A (en) * 1997-08-19 1999-11-23 Applied Materials, Inc. Dual damascene metallization
US5990011A (en) * 1997-09-18 1999-11-23 Micron Technology, Inc. Titanium aluminum alloy wetting layer for improved aluminum filling of damescene trenches
US6150691A (en) * 1997-12-19 2000-11-21 Micron Technology, Inc. Spacer patterned, high dielectric constant capacitor
US6028004A (en) * 1998-01-06 2000-02-22 International Business Machines Corporation Process for controlling the height of a stud intersecting an interconnect
US6025226A (en) * 1998-01-15 2000-02-15 International Business Machines Corporation Method of forming a capacitor and a capacitor formed using the method
US6081021A (en) * 1998-01-15 2000-06-27 International Business Machines Corporation Conductor-insulator-conductor structure
US6200896B1 (en) 1998-01-22 2001-03-13 Cypress Semiconductor Corporation Employing an acidic liquid and an abrasive surface to polish a semiconductor topography
US6204168B1 (en) 1998-02-02 2001-03-20 Applied Materials, Inc. Damascene structure fabricated using a layer of silicon-based photoresist material
US6140236A (en) * 1998-04-21 2000-10-31 Kabushiki Kaisha Toshiba High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring
US6218306B1 (en) 1998-04-22 2001-04-17 Applied Materials, Inc. Method of chemical mechanical polishing a metal layer
US6111301A (en) * 1998-04-24 2000-08-29 International Business Machines Corporation Interconnection with integrated corrosion stop
US6056869A (en) * 1998-06-04 2000-05-02 International Business Machines Corporation Wafer edge deplater for chemical mechanical polishing of substrates
US6200901B1 (en) 1998-06-10 2001-03-13 Micron Technology, Inc. Polishing polymer surfaces on non-porous CMP pads
US6245662B1 (en) 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
US6220934B1 (en) 1998-07-23 2001-04-24 Micron Technology, Inc. Method for controlling pH during planarization and cleaning of microelectronic substrates
FR2781922B1 (fr) * 1998-07-31 2001-11-23 Clariant France Sa Procede de polissage mecano-chimique d'une couche en un materiau a base de cuivre
US6287977B1 (en) 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US5972124A (en) 1998-08-31 1999-10-26 Advanced Micro Devices, Inc. Method for cleaning a surface of a dielectric material
US6232231B1 (en) 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6051496A (en) * 1998-09-17 2000-04-18 Taiwan Semiconductor Manufacturing Company Use of stop layer for chemical mechanical polishing of CU damascene
US6110648A (en) * 1998-09-17 2000-08-29 Taiwan Semiconductor Manufacturing Company Method of enclosing copper conductor in a dual damascene process
US6071814A (en) * 1998-09-28 2000-06-06 Taiwan Semiconductor Manufacturing Company Selective electroplating of copper for damascene process
US6566249B1 (en) 1998-11-09 2003-05-20 Cypress Semiconductor Corp. Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures
US6206756B1 (en) 1998-11-10 2001-03-27 Micron Technology, Inc. Tungsten chemical-mechanical polishing process using a fixed abrasive polishing pad and a tungsten layer chemical-mechanical polishing solution specifically adapted for chemical-mechanical polishing with a fixed abrasive pad
US6276996B1 (en) 1998-11-10 2001-08-21 Micron Technology, Inc. Copper chemical-mechanical polishing process using a fixed abrasive polishing pad and a copper layer chemical-mechanical polishing solution specifically adapted for chemical-mechanical polishing with a fixed abrasive pad
US6100168A (en) * 1998-11-16 2000-08-08 Industrial Technology Research Institute Location selective transmutation doping on silicon wafers using high energy deuterons
US6265308B1 (en) * 1998-11-30 2001-07-24 International Business Machines Corporation Slotted damascene lines for low resistive wiring lines for integrated circuit
US6181011B1 (en) 1998-12-29 2001-01-30 Kawasaki Steel Corporation Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same
US6114246A (en) * 1999-01-07 2000-09-05 Vlsi Technology, Inc. Method of using a polish stop film to control dishing during copper chemical mechanical polishing
EP1157059A1 (de) 1999-01-08 2001-11-28 The Dow Chemical Company Polymere mit einer niedriegen dielektrischen konstante, guten haftung und zähigkeit, und die daraus hergestellten gegenstände
US6174801B1 (en) 1999-03-05 2001-01-16 Taiwan Semiconductor Manufacturing Company E-beam direct writing to pattern step profiles of dielectric layers applied to fill poly via with poly line, contact with metal line, and metal via with metal line
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
US6395607B1 (en) * 1999-06-09 2002-05-28 Alliedsignal Inc. Integrated circuit fabrication method for self-aligned copper diffusion barrier
US6465376B2 (en) * 1999-08-18 2002-10-15 International Business Machines Corporation Method and structure for improving electromigration of chip interconnects
US6433429B1 (en) 1999-09-01 2002-08-13 International Business Machines Corporation Copper conductive line with redundant liner and method of making
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
US6344419B1 (en) 1999-12-03 2002-02-05 Applied Materials, Inc. Pulsed-mode RF bias for sidewall coverage improvement
US6295721B1 (en) * 1999-12-28 2001-10-02 Taiwan Semiconductor Manufacturing Company Metal fuse in copper dual damascene
US6303486B1 (en) * 2000-01-28 2001-10-16 Advanced Micro Devices, Inc. Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal
US6261960B1 (en) * 2000-04-06 2001-07-17 Advanced Micro Devices, Inc High density contacts having rectangular cross-section for dual damascene applications
US6554979B2 (en) 2000-06-05 2003-04-29 Applied Materials, Inc. Method and apparatus for bias deposition in a modulating electric field
US6635566B1 (en) * 2000-06-15 2003-10-21 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit
US6399512B1 (en) 2000-06-15 2002-06-04 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer
US8030172B1 (en) 2000-09-12 2011-10-04 Cypress Semiconductor Corporation Isolation technology for submicron semiconductor devices
US6373135B1 (en) * 2000-09-14 2002-04-16 Infineon Technologies Ag Semiconductor structure and method of fabrication
US6709874B2 (en) * 2001-01-24 2004-03-23 Infineon Technologies Ag Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation
US6969684B1 (en) 2001-04-30 2005-11-29 Cypress Semiconductor Corp. Method of making a planarized semiconductor structure
US6518641B2 (en) 2001-05-18 2003-02-11 International Business Machines Corporation Deep slit isolation with controlled void
JP2003023070A (ja) * 2001-07-05 2003-01-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6746591B2 (en) 2001-10-16 2004-06-08 Applied Materials Inc. ECP gap fill by modulating the voltate on the seed layer to increase copper concentration inside feature
KR100449320B1 (ko) * 2001-12-20 2004-09-18 동부전자 주식회사 반도체 소자의 소자 분리막 형성방법
US6943105B2 (en) * 2002-01-18 2005-09-13 International Business Machines Corporation Soft metal conductor and method of making
US6835616B1 (en) 2002-01-29 2004-12-28 Cypress Semiconductor Corporation Method of forming a floating metal structure in an integrated circuit
US7026235B1 (en) 2002-02-07 2006-04-11 Cypress Semiconductor Corporation Dual-damascene process and associated floating metal structures
US6828678B1 (en) 2002-03-29 2004-12-07 Silicon Magnetic Systems Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer
US6833575B2 (en) * 2002-08-29 2004-12-21 Micron Technology, Inc. Dopant barrier for doped glass in memory devices
US20040092102A1 (en) * 2002-11-12 2004-05-13 Sachem, Inc. Chemical mechanical polishing composition and method
US6975032B2 (en) * 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating
US6818285B2 (en) * 2002-12-31 2004-11-16 International Business Machines Corporation Composition and method to achieve reduced thermal expansion in polyarylene networks
JP4765076B2 (ja) * 2003-02-20 2011-09-07 ダウ グローバル テクノロジーズ エルエルシー ポリアリーレンの合成方法及びその方法により製造されたポリアリーレン
US20040174596A1 (en) * 2003-03-05 2004-09-09 Ricoh Optical Industries Co., Ltd. Polarization optical device and manufacturing method therefor
US7205228B2 (en) * 2003-06-03 2007-04-17 Applied Materials, Inc. Selective metal encapsulation schemes
US20060286306A1 (en) * 2005-06-17 2006-12-21 Asm Japan K.K. Method of producing advanced low dielectric constant film by UV light emission
US7789965B2 (en) 2006-09-19 2010-09-07 Asm Japan K.K. Method of cleaning UV irradiation chamber
US7960036B2 (en) * 2007-07-31 2011-06-14 International Business Machines Corporation Semiconductor structure and method of manufacturing same
US20090093135A1 (en) * 2007-10-04 2009-04-09 Asm Japan K.K. Semiconductor manufacturing apparatus and method for curing material with uv light
US20110101534A1 (en) * 2009-11-04 2011-05-05 International Business Machines Corporation Automated short length wire shape strapping and methods of fabricting the same
US8575000B2 (en) * 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
JP2013077711A (ja) 2011-09-30 2013-04-25 Sony Corp 半導体装置および半導体装置の製造方法
KR101992352B1 (ko) * 2012-09-25 2019-06-24 삼성전자주식회사 반도체 장치
US9379221B1 (en) * 2015-01-08 2016-06-28 International Business Machines Corporation Bottom-up metal gate formation on replacement metal gate finFET devices
US9588298B2 (en) 2015-06-04 2017-03-07 Elenion Technologies, Llc Edge coupler
US10886225B2 (en) 2018-03-05 2021-01-05 International Business Machines Corporation BEOL alternative metal interconnects: integration and process

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4035276A (en) * 1976-04-29 1977-07-12 Ibm Corporation Making coplanar layers of thin films
US4339305A (en) * 1981-02-05 1982-07-13 Rockwell International Corporation Planar circuit fabrication by plating and liftoff
JPS58110673A (ja) * 1981-12-23 1983-07-01 Hitachi Ltd 反応性スパツタリング装置
US4526631A (en) * 1984-06-25 1985-07-02 International Business Machines Corporation Method for forming a void free isolation pattern utilizing etch and refill techniques
JPH065673B2 (ja) * 1985-06-10 1994-01-19 日本電信電話株式会社 半導体装置とその製造方法
US4944836A (en) * 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US4702792A (en) * 1985-10-28 1987-10-27 International Business Machines Corporation Method of forming fine conductive lines, patterns and connectors
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4824802A (en) * 1986-02-28 1989-04-25 General Electric Company Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures
JPH01501985A (ja) * 1986-07-31 1989-07-06 アメリカン　テレフォン　アンド　テレグラフ　カムパニー 改良メタライゼーションを有する半導体デバイス
JPH0682660B2 (ja) * 1987-08-17 1994-10-19 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 導電性スタツドを形成する方法
US4956313A (en) * 1987-08-17 1990-09-11 International Business Machines Corporation Via-filling and planarization technique
US4824544A (en) * 1987-10-29 1989-04-25 International Business Machines Corporation Large area cathode lift-off sputter deposition device
US4847214A (en) * 1988-04-18 1989-07-11 Motorola Inc. Method for filling trenches from a seed layer
JP2561123B2 (ja) * 1988-04-19 1996-12-04 富士通株式会社 半導体装置の製造方法
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
JPH0283978A (ja) * 1988-09-20 1990-03-26 Nec Corp 半導体装置
US4992135A (en) * 1990-07-24 1991-02-12 Micron Technology, Inc. Method of etching back of tungsten layers on semiconductor wafers, and solution therefore

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ATE159615T1 (de) 1997-11-15
US5262354A (en) 1993-11-16
TW367599B (en) 1999-08-21
DE69314679T2 (de) 1998-04-02
EP0558004A2 (de) 1993-09-01
KR970006973B1 (ko) 1997-05-01
JPH0684826A (ja) 1994-03-25
CN1027610C (zh) 1995-02-08
HK1001601A1 (en) 1998-06-26
CN1076547A (zh) 1993-09-22
KR930018701A (ko) 1993-09-22
JP2989408B2 (ja) 1999-12-13
EP0558004B1 (de) 1997-10-22
EP0558004A3 (de) 1994-01-12

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