DE69314683D1 - Verfahren und Gerät zum Prüfen von Ein-/Ausgabeverbindungen des Randsteckverbinders einer Schaltkreiskarte mit Boundary Scan - Google Patents

Verfahren und Gerät zum Prüfen von Ein-/Ausgabeverbindungen des Randsteckverbinders einer Schaltkreiskarte mit Boundary Scan

Info

Publication number
DE69314683D1
DE69314683D1 DE69314683T DE69314683T DE69314683D1 DE 69314683 D1 DE69314683 D1 DE 69314683D1 DE 69314683 T DE69314683 T DE 69314683T DE 69314683 T DE69314683 T DE 69314683T DE 69314683 D1 DE69314683 D1 DE 69314683D1
Authority
DE
Germany
Prior art keywords
boundary scan
stem
output connections
input
chain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE69314683T
Other languages
English (en)
Other versions
DE69314683T2 (de
Inventor
Najmi Taher Jarwala
Chi Wang Yau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25291699&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69314683(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69314683D1 publication Critical patent/DE69314683D1/de
Application granted granted Critical
Publication of DE69314683T2 publication Critical patent/DE69314683T2/de
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318513—Test of Multi-Chip-Moduls
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
DE69314683T 1992-03-02 1993-02-17 Verfahren und Gerät zum Prüfen von Ein-/Ausgabeverbindungen des Randsteckverbinders einer Schaltkreiskarte mit Boundary Scan Revoked DE69314683T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84406092A 1992-03-02 1992-03-02

Publications (2)

Publication Number Publication Date
DE69314683D1 true DE69314683D1 (de) 1997-11-27
DE69314683T2 DE69314683T2 (de) 1998-02-19

Family

ID=25291699

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69314683T Revoked DE69314683T2 (de) 1992-03-02 1993-02-17 Verfahren und Gerät zum Prüfen von Ein-/Ausgabeverbindungen des Randsteckverbinders einer Schaltkreiskarte mit Boundary Scan

Country Status (6)

Country Link
US (1) US5331274A (de)
EP (1) EP0560500B1 (de)
JP (1) JPH0618620A (de)
KR (1) KR970002061B1 (de)
DE (1) DE69314683T2 (de)
TW (1) TW253097B (de)

Families Citing this family (24)

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US5390191A (en) * 1992-01-31 1995-02-14 Sony Corporation Apparatus and method for testing the interconnection between integrated circuits
GB9217728D0 (en) * 1992-08-20 1992-09-30 Texas Instruments Ltd Method of testing interconnections between integrated circuits in a circuit
JP2727930B2 (ja) * 1993-10-04 1998-03-18 日本電気株式会社 バウンダリスキャンテスト回路
JP3479653B2 (ja) * 1993-10-15 2003-12-15 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ テスト装置
US5513189A (en) * 1994-05-25 1996-04-30 Tandem Computers, Incorporated Boundary scan system with improved error reporting using sentinel bit patterns
US5574730A (en) * 1995-01-31 1996-11-12 Unisys Corporation Bussed test access port interface and method for testing and controlling system logic boards
US5604754A (en) * 1995-02-27 1997-02-18 International Business Machines Corporation Validating the synchronization of lock step operated circuits
US5852617A (en) * 1995-12-08 1998-12-22 Samsung Electronics Co., Ltd. Jtag testing of buses using plug-in cards with Jtag logic mounted thereon
US5774477A (en) 1995-12-22 1998-06-30 Lucent Technologies Inc. Method and apparatus for pseudorandom boundary-scan testing
DE69739438D1 (de) * 1996-02-06 2009-07-16 Ericsson Telefon Ab L M Anordnung und verfahren zur prüfung von integrierten schaltungseinrichtungen
US5787094A (en) * 1996-06-06 1998-07-28 International Business Machines Corporation Test and diagnostics for a self-timed parallel interface
US6539510B1 (en) * 1997-08-12 2003-03-25 Xilinx, Inc. Interface board for receiving modular interface cards
KR100512162B1 (ko) * 1998-03-31 2005-11-11 삼성전자주식회사 마이크로프로세서의에뮬레이션모드를위한바운더리스캔스탠다드인터페이스회로
US6441627B1 (en) * 1998-10-26 2002-08-27 Micron Technology, Inc. Socket test device for detecting characteristics of socket signals
US7071679B1 (en) 2003-05-23 2006-07-04 Xilinx, Inc. Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces
GB2405945B (en) * 2003-09-11 2006-10-25 Agilent Technologies Inc Printed circuit board assembly test apparatus
DE102008019861A1 (de) 2008-04-17 2009-10-29 Göpel electronic GmbH Verfahren zum Steuern von Anschlusspins eines emulationsfähigen Bausteins und Anordnung zur Durchführung des Verfahrens
JP5407257B2 (ja) * 2008-10-01 2014-02-05 富士通株式会社 回路試験装置及び回路試験システム
KR101222737B1 (ko) * 2010-09-27 2013-01-15 삼성전기주식회사 내장형 기판의 경계 스캔 테스트 장치 및 그 방법
RU2560967C1 (ru) * 2014-05-26 2015-08-20 Акционерное Общество "НПО "Орион" (АО "НПЦ "Орион") Способ коррекции топологии бис
DE102014010528A1 (de) 2014-07-18 2016-02-18 Mahle International Gmbh Pleuel sowie Baueinheit aus einem Kolben und einem Pleuel
CN108152720A (zh) * 2016-12-06 2018-06-12 英业达科技有限公司 测试非边界扫描芯片及其周边线路的系统及其方法
CN110007217B (zh) * 2019-05-22 2021-06-25 哈尔滨工业大学（威海） 一种低功耗边界扫描测试方法
TWI773402B (zh) * 2021-06-24 2022-08-01 英業達股份有限公司 提高邊界掃描測試的腳位測試涵蓋率系統及其方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3854125A (en) * 1971-06-15 1974-12-10 Instrumentation Engineering Automated diagnostic testing system
JPS60223250A (ja) * 1984-04-19 1985-11-07 Toshiba Corp 情報伝送装置
NL8502476A (nl) * 1985-09-11 1987-04-01 Philips Nv Werkwijze voor het testen van dragers met meerdere digitaal-werkende geintegreerde schakelingen, drager voorzien van zulke schakelingen, geintegreerde schakeling geschikt voor het aanbrengen op zo'n drager, en testinrichting voor het testen van zulke dragers.
US4710931A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Partitioned scan-testing system
NL8801362A (nl) * 1988-05-27 1989-12-18 Philips Nv Elektronische module bevattende een eerste substraatelement met een funktioneel deel, alsmede een tweede substraatelement voor het testen van een interkonnektiefunktie, voet bevattende zo een tweede substraatelement, substraatelement te gebruiken als zo een tweede substraatelement en elektronisch apparaat bevattende een plaat met gedrukte bedrading en ten minste twee zulke elektronische modules.
US4963824A (en) * 1988-11-04 1990-10-16 International Business Machines Corporation Diagnostics of a board containing a plurality of hybrid electronic components
GB8826921D0 (en) * 1988-11-17 1988-12-21 Datatrace Ltd Circuit testing
US5029166A (en) * 1989-05-31 1991-07-02 At&T Bell Laboratories Method and apparatus for testing circuit boards
US5056093A (en) * 1989-08-09 1991-10-08 Texas Instruments Incorporated System scan path architecture
US5115435A (en) * 1989-10-19 1992-05-19 Ncr Corporation Method and apparatus for bus executed boundary scanning
US5155732A (en) * 1990-10-09 1992-10-13 At&T Bell Laboratories Method and apparatus for data transfer to and from devices through a boundary-scan test access port
US5132635A (en) * 1991-03-05 1992-07-21 Ast Research, Inc. Serial testing of removable circuit boards on a backplane bus
US5173377A (en) * 1991-10-28 1992-12-22 Globe-Union Inc. Apparatus for electrically connecting cell modules of a metal oxide-hydrogen battery

Also Published As

Publication number Publication date
TW253097B (de) 1995-08-01
EP0560500A1 (de) 1993-09-15
KR970002061B1 (ko) 1997-02-21
KR930020167A (ko) 1993-10-19
EP0560500B1 (de) 1997-10-22
DE69314683T2 (de) 1998-02-19
JPH0618620A (ja) 1994-01-28
US5331274A (en) 1994-07-19

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8331 Complete revocation