DE69315451D1 - Chipträgerpackung für gedruckte Schaltungsplatte, wobei der Chip teilweise eingekapselt ist, und deren Herstellung - Google Patents

Chipträgerpackung für gedruckte Schaltungsplatte, wobei der Chip teilweise eingekapselt ist, und deren Herstellung

Info

Publication number
DE69315451D1
DE69315451D1 DE69315451T DE69315451T DE69315451D1 DE 69315451 D1 DE69315451 D1 DE 69315451D1 DE 69315451 T DE69315451 T DE 69315451T DE 69315451 T DE69315451 T DE 69315451T DE 69315451 D1 DE69315451 D1 DE 69315451D1
Authority
DE
Germany
Prior art keywords
chip
production
circuit board
printed circuit
carrier package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69315451T
Other languages
English (en)
Other versions
DE69315451T2 (de
Inventor
Chok J Chia
Seng-Sooi Lim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of DE69315451D1 publication Critical patent/DE69315451D1/de
Publication of DE69315451T2 publication Critical patent/DE69315451T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
DE69315451T 1992-02-07 1993-02-05 Chipträgerpackung für gedruckte Schaltungsplatte, wobei der Chip teilweise eingekapselt ist, und deren Herstellung Expired - Fee Related DE69315451T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/834,182 US5262927A (en) 1992-02-07 1992-02-07 Partially-molded, PCB chip carrier package

Publications (2)

Publication Number Publication Date
DE69315451D1 true DE69315451D1 (de) 1998-01-15
DE69315451T2 DE69315451T2 (de) 1998-06-18

Family

ID=25266299

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69315451T Expired - Fee Related DE69315451T2 (de) 1992-02-07 1993-02-05 Chipträgerpackung für gedruckte Schaltungsplatte, wobei der Chip teilweise eingekapselt ist, und deren Herstellung

Country Status (5)

Country Link
US (1) US5262927A (de)
EP (1) EP0554893B1 (de)
JP (1) JPH05343588A (de)
DE (1) DE69315451T2 (de)
ES (1) ES2112342T3 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7863088B2 (en) 2007-05-16 2011-01-04 Infineon Technologies Ag Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557150A (en) * 1992-02-07 1996-09-17 Lsi Logic Corporation Overmolded semiconductor package
US5652461A (en) * 1992-06-03 1997-07-29 Seiko Epson Corporation Semiconductor device with a convex heat sink
JP3572628B2 (ja) * 1992-06-03 2004-10-06 セイコーエプソン株式会社 半導体装置及びその製造方法
IT1255190B (it) * 1992-06-30 1995-10-20 Giuseppe Marchisi Dispositivo di interfaccia di comando per un motore elettrico
US5589668A (en) * 1993-05-12 1996-12-31 Hitachi Cable, Ltd. Multi-metal layer wiring tab tape carrier and process for fabricating the same
JP3362530B2 (ja) * 1993-12-16 2003-01-07 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
TW258829B (de) * 1994-01-28 1995-10-01 Ibm
DE69534124T2 (de) 1994-04-18 2006-05-04 Micron Technology, Inc. Verfahren und Vorrichtung zum automatischen Positionieren elektronischer Würfel in Bauteilverpackungen
JP2569400B2 (ja) * 1994-06-23 1997-01-08 九州日本電気株式会社 樹脂封止型半導体装置の製造方法
MY112145A (en) * 1994-07-11 2001-04-30 Ibm Direct attachment of heat sink attached directly to flip chip using flexible epoxy
JP3509274B2 (ja) * 1994-07-13 2004-03-22 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
JP3367299B2 (ja) * 1994-11-11 2003-01-14 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
US5615475A (en) * 1995-01-30 1997-04-01 Staktek Corporation Method of manufacturing an integrated package having a pair of die on a common lead frame
JP3542677B2 (ja) * 1995-02-27 2004-07-14 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
JP3309686B2 (ja) * 1995-03-17 2002-07-29 セイコーエプソン株式会社 樹脂封止型半導体装置及びその製造方法
US5566448A (en) * 1995-06-06 1996-10-22 International Business Machines Corporation Method of construction for multi-tiered cavities used in laminate carriers
JP2844558B2 (ja) * 1995-06-29 1999-01-06 信越ポリマー株式会社 チップ状半導体素子装着用の配線回路基板およびその製造方法
US5646444A (en) * 1995-10-05 1997-07-08 Motorola, Inc. Apparatus and method for mounting a component to an electrical circuit
US6072236A (en) 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US5940686A (en) * 1996-04-12 1999-08-17 Conexant Systems, Inc. Method for manufacturing multi-chip modules utilizing direct lead attach
US5679979A (en) * 1996-05-21 1997-10-21 Weingand; Christopher Dirk Surface mount package with heat transfer feature
AU6541996A (en) * 1996-06-24 1998-01-14 International Business Machines Corporation Stacked semiconductor device package
US5847929A (en) * 1996-06-28 1998-12-08 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
US6028355A (en) * 1998-06-16 2000-02-22 At&T Corp. Method and apparatus for dissipating heat from an enclosed printed wiring board
US6323060B1 (en) 1999-05-05 2001-11-27 Dense-Pac Microsystems, Inc. Stackable flex circuit IC package and method of making same
US6208519B1 (en) * 1999-08-31 2001-03-27 Micron Technology, Inc. Thermally enhanced semiconductor package
US6572387B2 (en) 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
US6262895B1 (en) 2000-01-13 2001-07-17 John A. Forthun Stackable chip package with flex carrier
US6306685B1 (en) * 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
US6608763B1 (en) 2000-09-15 2003-08-19 Staktek Group L.P. Stacking system and method
US6747879B2 (en) * 2001-02-28 2004-06-08 Andrew Corporation High power amplifier and chassis
US6760230B2 (en) * 2001-02-28 2004-07-06 Andrew Corporation Compact, high efficiency, high isolation power amplifier
US6462408B1 (en) 2001-03-27 2002-10-08 Staktek Group, L.P. Contact member stacking system and method
KR20030058942A (ko) * 2001-04-09 2003-07-07 가부시키가이샤 스미토모 긴조쿠 엘렉트로 디바이스 방열형 ｂｇａ 패키지 및 그 제조 방법
US7371609B2 (en) 2001-10-26 2008-05-13 Staktek Group L.P. Stacked module systems and methods
US7310458B2 (en) 2001-10-26 2007-12-18 Staktek Group L.P. Stacked module systems and methods
US20060255446A1 (en) 2001-10-26 2006-11-16 Staktek Group, L.P. Stacked modules and method
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US7485951B2 (en) 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
US6940729B2 (en) 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US7026708B2 (en) 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US20030234443A1 (en) 2001-10-26 2003-12-25 Staktek Group, L.P. Low profile stacking system and method
US7656678B2 (en) 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US7053478B2 (en) 2001-10-26 2006-05-30 Staktek Group L.P. Pitch change and chip scale stacking system
US6914324B2 (en) 2001-10-26 2005-07-05 Staktek Group L.P. Memory expansion and chip scale stacking system and method
US6956284B2 (en) 2001-10-26 2005-10-18 Staktek Group L.P. Integrated circuit stacking system and method
US7081373B2 (en) 2001-12-14 2006-07-25 Staktek Group, L.P. CSP chip stack with flex circuit
US6841029B2 (en) * 2003-03-27 2005-01-11 Advanced Cardiovascular Systems, Inc. Surface modification of expanded ultra high molecular weight polyethylene (eUHMWPE) for improved bondability
US7542304B2 (en) 2003-09-15 2009-06-02 Entorian Technologies, Lp Memory expansion and integrated circuit stacking system and method
US7309914B2 (en) 2005-01-20 2007-12-18 Staktek Group L.P. Inverted CSP stacking system and method
US7033861B1 (en) 2005-05-18 2006-04-25 Staktek Group L.P. Stacked module systems and method
KR100697624B1 (ko) * 2005-07-18 2007-03-22 삼성전자주식회사 접착제 흐름 제어를 위한 표면 구조를 가지는 패키지 기판및 이를 이용한 반도체 패키지
US7576995B2 (en) 2005-11-04 2009-08-18 Entorian Technologies, Lp Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area
US7605454B2 (en) 2006-01-11 2009-10-20 Entorian Technologies, Lp Memory card and method for devising
US7508058B2 (en) 2006-01-11 2009-03-24 Entorian Technologies, Lp Stacked integrated circuit module
US7508069B2 (en) 2006-01-11 2009-03-24 Entorian Technologies, Lp Managed memory component
US7608920B2 (en) 2006-01-11 2009-10-27 Entorian Technologies, Lp Memory card and method for devising
US7304382B2 (en) 2006-01-11 2007-12-04 Staktek Group L.P. Managed memory component
US7741706B2 (en) 2006-09-29 2010-06-22 Microsemi Corporation Plastic surface mount large area power device
US7468553B2 (en) 2006-10-20 2008-12-23 Entorian Technologies, Lp Stackable micropackages and stacked modules
US7417310B2 (en) 2006-11-02 2008-08-26 Entorian Technologies, Lp Circuit module having force resistant construction
US8829663B2 (en) 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through
DE102009045063C5 (de) * 2009-09-28 2017-06-01 Infineon Technologies Ag Leistungshalbleitermodul mit angespritztem Kühlkörper, Leistungshalbleitermodulsystem und Verfahren zur Herstellung eines Leistungshalbleitermoduls

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3405441A (en) * 1965-08-10 1968-10-15 Corning Glass Works Method of enclosing an electrical device
US3909838A (en) * 1973-08-01 1975-09-30 Signetics Corp Encapsulated integrated circuit and method
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
US4300153A (en) * 1977-09-22 1981-11-10 Sharp Kabushiki Kaisha Flat shaped semiconductor encapsulation
FR2439478A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Boitier plat pour dispositifs a circuits integres
US4330790A (en) * 1980-03-24 1982-05-18 National Semiconductor Corporation Tape operated semiconductor device packaging
US4363076A (en) * 1980-12-29 1982-12-07 Honeywell Information Systems Inc. Integrated circuit package
JPS57147260A (en) * 1981-03-05 1982-09-11 Matsushita Electronics Corp Manufacture of resin-sealed semiconductor device and lead frame used therefor
US4594770A (en) * 1982-07-15 1986-06-17 Olin Corporation Method of making semiconductor casing
JPS5966157A (ja) * 1982-10-08 1984-04-14 Fujitsu Ltd 半導体装置及びその製造方法
US4872825A (en) * 1984-05-23 1989-10-10 Ross Milton I Method and apparatus for making encapsulated electronic circuit devices
JP2502511B2 (ja) * 1986-02-06 1996-05-29 日立マクセル株式会社 半導体装置の製造方法
US4890152A (en) * 1986-02-14 1989-12-26 Matsushita Electric Works, Ltd. Plastic molded chip carrier package and method of fabricating the same
FR2598258B1 (fr) * 1986-04-30 1988-10-07 Aix Les Bains Composants Procede d'encapsulation de circuits integres.
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
US4874722A (en) * 1987-04-16 1989-10-17 Texas Instruments Incorporated Process of packaging a semiconductor device with reduced stress forces
KR970003915B1 (ko) * 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
JPH01129431A (ja) * 1987-11-16 1989-05-22 Sharp Corp 半導体チップ実装方式
US4969225A (en) * 1988-06-27 1990-11-13 James B. Andres Bathing and cleansing article
US4913930A (en) * 1988-06-28 1990-04-03 Wacker Silicones Corporation Method for coating semiconductor components on a dielectric film
EP0351581A1 (de) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG Hochintegrierte Schaltung sowie Verfahren zu deren Herstellung
DE3911711A1 (de) * 1989-04-10 1990-10-11 Ibm Modul-aufbau mit integriertem halbleiterchip und chiptraeger
FR2651923B1 (fr) * 1989-09-14 1994-06-17 Peugeot Circuit integre de puissance.
US5012386A (en) * 1989-10-27 1991-04-30 Motorola, Inc. High performance overmolded electronic package
US5025114A (en) * 1989-10-30 1991-06-18 Olin Corporation Multi-layer lead frames for integrated circuit packages
US5051813A (en) * 1989-12-19 1991-09-24 Lsi Logic Corporation Plastic-packaged semiconductor device having lead support and alignment structure
JP2875562B2 (ja) * 1989-12-22 1999-03-31 沖電気工業株式会社 半導体装置及びその製造方法
JP2740976B2 (ja) * 1990-01-09 1998-04-15 イビデン株式会社 電子部品塔載用基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7863088B2 (en) 2007-05-16 2011-01-04 Infineon Technologies Ag Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound

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US5262927A (en) 1993-11-16
EP0554893A3 (de) 1994-03-23
DE69315451T2 (de) 1998-06-18
ES2112342T3 (es) 1998-04-01
EP0554893B1 (de) 1997-12-03
EP0554893A2 (de) 1993-08-11
JPH05343588A (ja) 1993-12-24

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