DE69315976D1 - Pegelverschiebungsschaltung - Google Patents

Pegelverschiebungsschaltung

Info

Publication number
DE69315976D1
DE69315976D1 DE69315976T DE69315976T DE69315976D1 DE 69315976 D1 DE69315976 D1 DE 69315976D1 DE 69315976 T DE69315976 T DE 69315976T DE 69315976 T DE69315976 T DE 69315976T DE 69315976 D1 DE69315976 D1 DE 69315976D1
Authority
DE
Germany
Prior art keywords
shift circuit
level shift
level
circuit
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69315976T
Other languages
English (en)
Other versions
DE69315976T2 (de
Inventor
Miyo Miyashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE69315976D1 publication Critical patent/DE69315976D1/de
Application granted granted Critical
Publication of DE69315976T2 publication Critical patent/DE69315976T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00369Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
DE69315976T 1993-02-19 1993-08-31 Pegelverschiebungsschaltung Expired - Fee Related DE69315976T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02997993A JP3315178B2 (ja) 1993-02-19 1993-02-19 レベルシフト回路

Publications (2)

Publication Number Publication Date
DE69315976D1 true DE69315976D1 (de) 1998-02-05
DE69315976T2 DE69315976T2 (de) 1998-04-16

Family

ID=12291089

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69315976T Expired - Fee Related DE69315976T2 (de) 1993-02-19 1993-08-31 Pegelverschiebungsschaltung

Country Status (4)

Country Link
US (1) US6051993A (de)
EP (1) EP0612152B1 (de)
JP (1) JP3315178B2 (de)
DE (1) DE69315976T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3450257B2 (ja) 2000-02-28 2003-09-22 Nec化合物デバイス株式会社 アクティブ・バイアス回路
US6483347B1 (en) 2001-07-11 2002-11-19 Micron Technology, Inc. High speed digital signal buffer and method
JP2009033637A (ja) * 2007-07-30 2009-02-12 Panasonic Corp レベル変換回路
US20090046532A1 (en) * 2007-08-17 2009-02-19 Infineon Technologies Ag Supply Voltage for Memory Device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4068140A (en) * 1976-12-27 1978-01-10 Texas Instruments Incorporated MOS source follower circuit
JPS57176837A (en) * 1981-04-24 1982-10-30 Hitachi Ltd Level shift circuit
JPS5892140A (ja) * 1981-11-26 1983-06-01 Mitsubishi Electric Corp 半導体論理回路装置
JPS5999819A (ja) * 1982-11-27 1984-06-08 Hitachi Ltd 入力インタ−フエイス回路
US4584492A (en) * 1984-08-06 1986-04-22 Intel Corporation Temperature and process stable MOS input buffer
JPS61142820A (ja) * 1984-10-22 1986-06-30 ジガビツト・ロジツク・インコ−ポレイテツド コンデンサダイオ−ドfet論理回路
JPS61103223A (ja) * 1984-10-26 1986-05-21 Mitsubishi Electric Corp 定電圧発生回路
US4717836A (en) * 1986-02-04 1988-01-05 Burr-Brown Corporation CMOS input level shifting circuit with temperature-compensating n-channel field effect transistor structure
JPS62262514A (ja) * 1986-05-08 1987-11-14 Nec Corp 集積回路
JPS63268303A (ja) * 1987-04-24 1988-11-07 Nec Corp レベルシフト回路
US4844563A (en) * 1987-05-19 1989-07-04 Gazelle Microcircuits, Inc. Semiconductor integrated circuit compatible with compound standard logic signals
JPH0732358B2 (ja) * 1987-06-12 1995-04-10 日本電気株式会社 レベルシフト回路
JP2574859B2 (ja) * 1988-03-16 1997-01-22 株式会社日立製作所 Fet論理回路
JP2562831B2 (ja) * 1988-06-03 1996-12-11 富士通株式会社 レベル変換回路
JP2751422B2 (ja) * 1988-06-27 1998-05-18 日本電気株式会社 半導体装置
JP2666435B2 (ja) * 1988-11-30 1997-10-22 日本電気株式会社 温度補償レベルシフト回路
JPH02256318A (ja) * 1989-03-29 1990-10-17 Sumitomo Electric Ind Ltd レベルシフト回路
US5225718A (en) * 1989-05-29 1993-07-06 Kabushiki Kaisha Toshiba Standard-cell type semiconductor logic lsi with logical amplitude enhancer
JPH0414314A (ja) * 1990-05-08 1992-01-20 Toshiba Corp ソース電極結合形論理回路

Also Published As

Publication number Publication date
DE69315976T2 (de) 1998-04-16
EP0612152A2 (de) 1994-08-24
US6051993A (en) 2000-04-18
EP0612152A3 (de) 1995-02-08
EP0612152B1 (de) 1997-12-29
JP3315178B2 (ja) 2002-08-19
JPH06244659A (ja) 1994-09-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee