DE69322051T2 - Wartezustandsteuerung auf einem Informationverarbeitungssystembus - Google Patents

Wartezustandsteuerung auf einem Informationverarbeitungssystembus

Info

Publication number
DE69322051T2
DE69322051T2 DE69322051T DE69322051T DE69322051T2 DE 69322051 T2 DE69322051 T2 DE 69322051T2 DE 69322051 T DE69322051 T DE 69322051T DE 69322051 T DE69322051 T DE 69322051T DE 69322051 T2 DE69322051 T2 DE 69322051T2
Authority
DE
Germany
Prior art keywords
information processing
processing system
system bus
state control
wait state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69322051T
Other languages
English (en)
Other versions
DE69322051D1 (de
Inventor
Toshiya Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hudson Soft Co Ltd
Original Assignee
Hudson Soft Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP4284984A external-priority patent/JPH06180986A/ja
Priority claimed from JP28498392A external-priority patent/JPH06180647A/ja
Priority claimed from JP4284987A external-priority patent/JPH06180673A/ja
Priority claimed from JP28498692A external-priority patent/JPH06180681A/ja
Priority claimed from JP4293767A external-priority patent/JPH06180984A/ja
Application filed by Hudson Soft Co Ltd filed Critical Hudson Soft Co Ltd
Publication of DE69322051D1 publication Critical patent/DE69322051D1/de
Application granted granted Critical
Publication of DE69322051T2 publication Critical patent/DE69322051T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1689Synchronisation and timing concerns
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
DE69322051T 1992-10-01 1993-09-29 Wartezustandsteuerung auf einem Informationverarbeitungssystembus Expired - Fee Related DE69322051T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP4284984A JPH06180986A (ja) 1992-10-01 1992-10-01 メモリコントローラユニット
JP28498392A JPH06180647A (ja) 1992-10-01 1992-10-01 バス転送速度調整機能付き中央処理装置
JP4284987A JPH06180673A (ja) 1992-10-01 1992-10-01 情報処理装置
JP28498692A JPH06180681A (ja) 1992-10-01 1992-10-01 中央処理装置
JP4293767A JPH06180984A (ja) 1992-10-07 1992-10-07 中央処理装置

Publications (2)

Publication Number Publication Date
DE69322051D1 DE69322051D1 (de) 1998-12-17
DE69322051T2 true DE69322051T2 (de) 1999-06-24

Family

ID=27530739

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322051T Expired - Fee Related DE69322051T2 (de) 1992-10-01 1993-09-29 Wartezustandsteuerung auf einem Informationverarbeitungssystembus

Country Status (5)

Country Link
US (2) US5822753A (de)
EP (1) EP0590967B1 (de)
CA (1) CA2107437A1 (de)
DE (1) DE69322051T2 (de)
TW (1) TW390446U (de)

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TW390446U (en) * 1992-10-01 2000-05-11 Hudson Soft Co Ltd Information processing system
JP4154010B2 (ja) * 1997-07-17 2008-09-24 キヤノン株式会社 メモリ制御装置およびメモリ制御方法
US6928653B1 (en) 1997-11-06 2005-08-09 United Video Properties, Inc. Interactive electronic television program guide with database configurability
US6728862B1 (en) * 2000-05-22 2004-04-27 Gazelle Technology Corporation Processor array and parallel data processing methods
JP2002023881A (ja) * 2000-07-12 2002-01-25 Sony Corp 情報処理装置および方法、並びにプログラム格納媒体
US7032119B2 (en) * 2000-09-27 2006-04-18 Amphus, Inc. Dynamic power and workload management for multi-server system
US6889335B2 (en) * 2001-04-07 2005-05-03 Hewlett-Packard Development Company, L.P. Memory controller receiver circuitry with tri-state noise immunity
US6678811B2 (en) * 2001-04-07 2004-01-13 Hewlett-Packard Development Company, L.P. Memory controller with 1X/MX write capability
US6625702B2 (en) * 2001-04-07 2003-09-23 Hewlett-Packard Development Company, L.P. Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices
US6633965B2 (en) * 2001-04-07 2003-10-14 Eric M. Rentschler Memory controller with 1×/M× read capability
US20030196126A1 (en) * 2002-04-11 2003-10-16 Fung Henry T. System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment
DE102005054347A1 (de) * 2005-11-15 2007-05-24 Atmel Duisburg Gmbh Elektronische Schaltung und Verfahren zum Betreiben einer elektronischen Schaltung
US7539050B2 (en) * 2006-11-22 2009-05-26 Qimonda North America Corp. Resistive memory including refresh operation
KR102036514B1 (ko) * 2015-07-13 2019-10-28 엘에스산전 주식회사 메모리 소자를 이용한 데이터 엑세스 장치

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US3704453A (en) * 1971-02-23 1972-11-28 Ibm Catenated files
EP0172493B1 (de) * 1980-03-19 1990-11-14 Kabushiki Kaisha Toshiba Datenverarbeitungssystem
US4556952A (en) * 1981-08-12 1985-12-03 International Business Machines Corporation Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
IT1142074B (it) * 1981-11-24 1986-10-08 Honeywell Inf Systems Sistema di elaborazione dati con allocazione automatica dell'indirizzo in una memoria modulare
US4509113A (en) * 1982-02-02 1985-04-02 International Business Machines Corporation Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation
EP0164735A3 (de) * 1984-06-11 1988-11-09 Nec Corporation Mikroprozessor mit Erfrischungsschaltung für dynamischen Speicher
JPS62190999U (de) * 1986-05-23 1987-12-04
US4841435A (en) * 1986-10-29 1989-06-20 Saxpy Computer Corporation Data alignment system for random and block transfers of embedded subarrays of an array onto a system bus
US5325513A (en) * 1987-02-23 1994-06-28 Kabushiki Kaisha Toshiba Apparatus for selectively accessing different memory types by storing memory correlation information in preprocessing mode and using the information in processing mode
US4908789A (en) * 1987-04-01 1990-03-13 International Business Machines Corporation Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range
KR890702135A (ko) * 1987-07-23 1989-12-22 원본미기재 컴퓨터 시스템
US4899272A (en) * 1987-10-23 1990-02-06 Chips & Technologies, Inc. Addressing multiple types of memory devices
US5040153A (en) * 1987-10-23 1991-08-13 Chips And Technologies, Incorporated Addressing multiple types of memory devices
US5129069A (en) * 1989-01-24 1992-07-07 Zenith Data Systems Corporation Method and apparatus for automatic memory configuration by a computer
US5131081A (en) * 1989-03-23 1992-07-14 North American Philips Corp., Signetics Div. System having a host independent input/output processor for controlling data transfer between a memory and a plurality of i/o controllers
US5241642A (en) * 1989-09-28 1993-08-31 Pixel Semiconductor, Inc. Image memory controller for controlling multiple memories and method of operation
EP0419869A3 (en) * 1989-09-29 1992-06-03 Kabushiki Kaisha Toshiba Personal computer for accessing two types of extended memories having different memory capacities
JPH03167649A (ja) * 1989-11-28 1991-07-19 Nec Corp ウエイト・サイクル制御装置
JP3225531B2 (ja) * 1990-05-15 2001-11-05 セイコーエプソン株式会社 メモリカード
US5394541A (en) * 1990-07-17 1995-02-28 Sun Microsystems, Inc. Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals
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US5522064A (en) * 1990-10-01 1996-05-28 International Business Machines Corporation Data processing apparatus for dynamically setting timings in a dynamic memory system
US5253355A (en) * 1990-11-13 1993-10-12 Compaq Computer Corporation Apparatus and method for developing wait states during addressing operation by using unused address bits
US5448710A (en) * 1991-02-26 1995-09-05 Hewlett-Packard Company Dynamically configurable interface cards with variable memory size
US5386537A (en) * 1991-03-28 1995-01-31 Minolta Camera Kabushiki Kaisha System with reduced instruction set processor accessing plural memories at different speeds using bank interleaving
US5630163A (en) * 1991-08-09 1997-05-13 Vadem Corporation Computer having a single bus supporting multiple bus architectures operating with different bus parameters
US5347641A (en) * 1991-08-30 1994-09-13 Waferscale Integration, Inc. Page register with a don't care function
US5404543A (en) * 1992-05-29 1995-04-04 International Business Machines Corporation Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes
US5379400A (en) * 1992-08-07 1995-01-03 International Business Machines Corp. Method and system for determining memory refresh rate
US5418924A (en) * 1992-08-31 1995-05-23 Hewlett-Packard Company Memory controller with programmable timing
US5307320A (en) * 1992-09-23 1994-04-26 Intel Corporation High integration DRAM controller
TW390446U (en) * 1992-10-01 2000-05-11 Hudson Soft Co Ltd Information processing system
US5740404A (en) * 1993-09-27 1998-04-14 Hitachi America Limited Digital signal processor with on-chip select decoder and wait state generator

Also Published As

Publication number Publication date
CA2107437A1 (en) 1994-04-02
DE69322051D1 (de) 1998-12-17
US6065132A (en) 2000-05-16
EP0590967A1 (de) 1994-04-06
TW390446U (en) 2000-05-11
US5822753A (en) 1998-10-13
EP0590967B1 (de) 1998-11-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee