DE69324651D1 - Mikrocomputer und Mikrocomputersystem - Google Patents

Mikrocomputer und Mikrocomputersystem

Info

Publication number
DE69324651D1
DE69324651D1 DE69324651T DE69324651T DE69324651D1 DE 69324651 D1 DE69324651 D1 DE 69324651D1 DE 69324651 T DE69324651 T DE 69324651T DE 69324651 T DE69324651 T DE 69324651T DE 69324651 D1 DE69324651 D1 DE 69324651D1
Authority
DE
Germany
Prior art keywords
microcomputers
microcomputer systems
microcomputer
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69324651T
Other languages
English (en)
Other versions
DE69324651T2 (de
Inventor
Shumpei Kawasaki
Kaoru Fukada
Mitsuru Watabe
Kouki Noguchi
Kiyoshi Matsubara
Isamu Mochizuki
Kazufumi Suzukawa
Shigeki Masumura
Yasushi Akao
Eiji Sakakibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd Tokio/tokyo Jp Hitachi Ulsi System
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Microcomputer System Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Microcomputer System Ltd, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Publication of DE69324651D1 publication Critical patent/DE69324651D1/de
Application granted granted Critical
Publication of DE69324651T2 publication Critical patent/DE69324651T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/786Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using a single memory module
DE69324651T 1992-11-06 1993-10-25 Mikrocomputer und Mikrocomputersystem Expired - Fee Related DE69324651T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4322598A JPH06150023A (ja) 1992-11-06 1992-11-06 マイクロコンピュータ及びマイクロコンピュータシステム

Publications (2)

Publication Number Publication Date
DE69324651D1 true DE69324651D1 (de) 1999-06-02
DE69324651T2 DE69324651T2 (de) 1999-12-30

Family

ID=18145497

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69324651T Expired - Fee Related DE69324651T2 (de) 1992-11-06 1993-10-25 Mikrocomputer und Mikrocomputersystem

Country Status (5)

Country Link
US (3) US5530965A (de)
EP (1) EP0597307B1 (de)
JP (1) JPH06150023A (de)
KR (1) KR100279780B1 (de)
DE (1) DE69324651T2 (de)

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0140571B1 (ko) * 1995-01-19 1998-07-01 김광호 버스제어수단을 구비한 다중프로세서시스템
GB2309559B (en) * 1996-01-27 2000-01-26 Motorola Israel Ltd Microprocessor and system
US5890196A (en) * 1996-03-28 1999-03-30 Motorola, Inc. Method and apparatus for performing page mode accesses
WO1998007099A1 (en) * 1996-08-14 1998-02-19 Advanced Micro Devices, Inc. A microcontroller including an internal memory unit and circuitry to generate an associated enable signal
US6031767A (en) * 1996-09-18 2000-02-29 International Business Machines Corporation Integrated circuit I/O interface that uses excess data I/O pin bandwidth to input control signals or output status information
US6260101B1 (en) 1997-03-07 2001-07-10 Advanced Micro Devices, Inc. Microcontroller having dedicated hardware for memory address space expansion supporting both static and dynamic memory devices
US6327640B1 (en) 1997-03-07 2001-12-04 Advanced Micro Devices, Inc. Overlapping peripheral chip select space with DRAM on a microcontroller with an integrated DRAM controller
US6016537A (en) * 1997-03-07 2000-01-18 Advanced Micro Devices, Inc. Method and apparatus for address multiplexing to support variable DRAM sizes
US5966736A (en) * 1997-03-07 1999-10-12 Advanced Micro Devices, Inc. Multiplexing DRAM control signals and chip select on a processor
US6212599B1 (en) * 1997-11-26 2001-04-03 Intel Corporation Method and apparatus for a memory control system including a secondary controller for DRAM refresh during sleep mode
US6862563B1 (en) 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
US20060168431A1 (en) * 1998-10-14 2006-07-27 Peter Warnes Method and apparatus for jump delay slot control in a pipelined processor
SE512773C2 (sv) * 1998-10-28 2000-05-08 Imsys Ab Metod och anordning för kontroll/access av DRAM-minnen
JP2001067335A (ja) * 1999-06-23 2001-03-16 Denso Corp マイクロコンピュータ
US20020054790A1 (en) * 1999-08-19 2002-05-09 Rockwood Retaining Walls, Inc. Block with multifaceted bottom surface
US6591369B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics, Ltd. System and method for communicating with an integrated circuit
US7000078B1 (en) 1999-10-01 2006-02-14 Stmicroelectronics Ltd. System and method for maintaining cache coherency in a shared memory system
US6779145B1 (en) 1999-10-01 2004-08-17 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6449712B1 (en) 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US7793261B1 (en) 1999-10-01 2010-09-07 Stmicroelectronics Limited Interface for transferring debug information
US6349371B1 (en) 1999-10-01 2002-02-19 Stmicroelectronics Ltd. Circuit for storing information
US6351803B2 (en) 1999-10-01 2002-02-26 Hitachi Ltd. Mechanism for power efficient processing in a pipeline processor
US6732307B1 (en) 1999-10-01 2004-05-04 Hitachi, Ltd. Apparatus and method for storing trace information
US6629207B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
US6567932B2 (en) 1999-10-01 2003-05-20 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6615370B1 (en) 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
US6530047B1 (en) 1999-10-01 2003-03-04 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6918065B1 (en) 1999-10-01 2005-07-12 Hitachi, Ltd. Method for compressing and decompressing trace information
US6684348B1 (en) 1999-10-01 2004-01-27 Hitachi, Ltd. Circuit for processing trace information
US6693914B1 (en) 1999-10-01 2004-02-17 Stmicroelectronics, Inc. Arbitration mechanism for packet transmission
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6633971B2 (en) 1999-10-01 2003-10-14 Hitachi, Ltd. Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
US6408381B1 (en) 1999-10-01 2002-06-18 Hitachi, Ltd. Mechanism for fast access to control space in a pipeline processor
US6542983B1 (en) 1999-10-01 2003-04-01 Hitachi, Ltd. Microcomputer/floating point processor interface and method
US6859891B2 (en) 1999-10-01 2005-02-22 Stmicroelectronics Limited Apparatus and method for shadowing processor information
US6772325B1 (en) * 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
US7266728B1 (en) 1999-10-01 2007-09-04 Stmicroelectronics Ltd. Circuit for monitoring information on an interconnect
US6546480B1 (en) 1999-10-01 2003-04-08 Hitachi, Ltd. Instructions for arithmetic operations on vectored data
US6665816B1 (en) 1999-10-01 2003-12-16 Stmicroelectronics Limited Data shift register
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd 2つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6601189B1 (en) 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6820195B1 (en) 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
US6460174B1 (en) 1999-10-01 2002-10-01 Stmicroelectronics, Ltd. Methods and models for use in designing an integrated circuit
US6598177B1 (en) 1999-10-01 2003-07-22 Stmicroelectronics Ltd. Monitoring error conditions in an integrated circuit
US7072817B1 (en) 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
US6826191B1 (en) 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US6457118B1 (en) 1999-10-01 2002-09-24 Hitachi Ltd Method and system for selecting and using source operands in computer system instructions
US6434665B1 (en) 1999-10-01 2002-08-13 Stmicroelectronics, Inc. Cache memory store buffer
US7260745B1 (en) 1999-10-01 2007-08-21 Stmicroelectronics Ltd. Detection of information on an interconnect
US6463553B1 (en) 1999-10-01 2002-10-08 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6590907B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics Ltd. Integrated circuit with additional ports
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6298394B1 (en) 1999-10-01 2001-10-02 Stmicroelectronics, Ltd. System and method for capturing information on an interconnect in an integrated circuit
US6629115B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method and apparatus for manipulating vectored data
US6928073B2 (en) * 1999-10-01 2005-08-09 Stmicroelectronics Ltd. Integrated circuit implementing packet transmission
US6412047B2 (en) 1999-10-01 2002-06-25 Stmicroelectronics, Inc. Coherency protocol
US6496905B1 (en) 1999-10-01 2002-12-17 Hitachi, Ltd. Write buffer with burst capability
US6701405B1 (en) 1999-10-01 2004-03-02 Hitachi, Ltd. DMA handshake protocol
US6487683B1 (en) 1999-10-01 2002-11-26 Stmicroelectronics Limited Microcomputer debug architecture and method
US6557119B1 (en) 1999-10-01 2003-04-29 Stmicroelectronics Limited Microcomputer debug architecture and method
US6553460B1 (en) 1999-10-01 2003-04-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6502210B1 (en) 1999-10-01 2002-12-31 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6574651B1 (en) 1999-10-01 2003-06-03 Hitachi, Ltd. Method and apparatus for arithmetic operation on vectored data
US6557096B1 (en) 1999-10-25 2003-04-29 Intel Corporation Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
US6408376B1 (en) * 1999-10-25 2002-06-18 Intel Corporation Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously
US6330660B1 (en) 1999-10-25 2001-12-11 Vxtel, Inc. Method and apparatus for saturated multiplication and accumulation in an application specific signal processor
US6832306B1 (en) 1999-10-25 2004-12-14 Intel Corporation Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions
US6563746B2 (en) * 1999-11-09 2003-05-13 Fujitsu Limited Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode
US6732203B2 (en) * 2000-01-31 2004-05-04 Intel Corporation Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
AU2001243463A1 (en) * 2000-03-10 2001-09-24 Arc International Plc Memory interface and method of interfacing between functional entities
US7284064B1 (en) 2000-03-21 2007-10-16 Intel Corporation Method and apparatus to determine broadcast content and scheduling in a broadcast system
JP3845814B2 (ja) * 2000-08-10 2006-11-15 株式会社テルミナス・テクノロジー 連想メモリとその検索方法及びルータとネットワークシステム
US7003093B2 (en) * 2000-09-08 2006-02-21 Intel Corporation Tone detection for integrated telecommunications processing
US20020116186A1 (en) * 2000-09-09 2002-08-22 Adam Strauss Voice activity detector for integrated telecommunications processing
US7275254B1 (en) 2000-11-21 2007-09-25 Intel Corporation Method and apparatus for determining and displaying the service level of a digital television broadcast signal
US6890919B2 (en) * 2001-06-26 2005-05-10 Shitij Kapur Atypical antipsychotic agents having low affinity for the D2 receptor
US6625716B2 (en) * 2001-06-28 2003-09-23 Intel Corporation Method apparatus, and system for efficient address and data protocol for a memory
US8943540B2 (en) 2001-09-28 2015-01-27 Intel Corporation Method and apparatus to provide a personalized channel
US20030219113A1 (en) * 2002-05-21 2003-11-27 Bershad Neil J. Echo canceller with double-talk and channel impulse response adaptation
JP4617282B2 (ja) * 2006-08-31 2011-01-19 富士通株式会社 負荷発生装置及び負荷試験方法
US7598166B2 (en) * 2006-09-08 2009-10-06 International Business Machines Corporation Dielectric layers for metal lines in semiconductor chips
US8127113B1 (en) 2006-12-01 2012-02-28 Synopsys, Inc. Generating hardware accelerators and processor offloads
TWI367486B (en) * 2007-12-25 2012-07-01 Ind Tech Res Inst Memory device and refresh method thereof
JP2010113765A (ja) * 2008-11-06 2010-05-20 Elpida Memory Inc 半導体記憶装置
US8074033B1 (en) 2009-01-12 2011-12-06 Ixys Ch Gmbh Cooperating memory controllers that share data bus terminals for accessing wide external devices
US9152423B2 (en) * 2011-03-25 2015-10-06 Avaya Inc. Method and apparatus for efficient loop instruction execution using bit vector scanning

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4332008A (en) * 1976-03-09 1982-05-25 Zilog, Inc. Microprocessor apparatus and method
JPH0642263B2 (ja) 1984-11-26 1994-06-01 株式会社日立製作所 デ−タ処理装置
JPH0792792B2 (ja) * 1985-08-23 1995-10-09 株式会社日立製作所 デ−タ処理装置
US4757504A (en) * 1986-04-21 1988-07-12 Texas Instruments Incorporated Polyphase parity generator circuit
US5048012A (en) * 1987-04-03 1991-09-10 Advanced Micro Devices, Inc. Data link controller with flexible multiplexer
US5151986A (en) * 1987-08-27 1992-09-29 Motorola, Inc. Microcomputer with on-board chip selects and programmable bus stretching
US5086407A (en) * 1989-06-05 1992-02-04 Mcgarity Ralph C Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
US5754886A (en) * 1989-08-29 1998-05-19 Hitachi, Ltd. Controller for supplying multiplexed or non-multiplexed address signals to different types of dynamic random access memories
JP3024767B2 (ja) * 1989-08-29 2000-03-21 株式会社日立製作所 アドレス供給システム
JPH0731850B2 (ja) * 1989-08-31 1995-04-10 日本ビクター株式会社 磁気記録再生装置のつなぎ撮り装置
JPH0398145A (ja) * 1989-09-11 1991-04-23 Hitachi Ltd マイクロプロセッサ
DE69123987T2 (de) * 1990-01-31 1997-04-30 Hewlett Packard Co Stossbetrieb für Mikroprozessor mit externem Systemspeicher
EP0518488A1 (de) * 1991-06-12 1992-12-16 Advanced Micro Devices, Inc. Busschnittstelle und Verarbeitungssystem
US5262998A (en) * 1991-08-14 1993-11-16 Micron Technology, Inc. Dynamic random access memory with operational sleep mode
US5262991A (en) * 1991-11-22 1993-11-16 Zilog, Inc. Device with multiplexed and non-multiplexed address and data I/O capability
WO1993012480A1 (en) * 1991-12-17 1993-06-24 Compaq Computer Corporation Apparatus for reducing computer system power consumption
US5414827A (en) * 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush

Also Published As

Publication number Publication date
US5987589A (en) 1999-11-16
EP0597307B1 (de) 1999-04-28
KR940012150A (ko) 1994-06-22
DE69324651T2 (de) 1999-12-30
US5530965A (en) 1996-06-25
KR100279780B1 (ko) 2001-02-01
EP0597307A1 (de) 1994-05-18
US5748977A (en) 1998-05-05
JPH06150023A (ja) 1994-05-31

Similar Documents

Publication Publication Date Title
DE69324651T2 (de) Mikrocomputer und Mikrocomputersystem
DE69318944T2 (de) Lagebestimmungssystem und Verfahren
DE69637170D1 (de) Zonenbasierte güterordnung und steuersystem
DE69526899T2 (de) Radarmodul und Radarsystem
DE69319588D1 (de) Kommunikationsbus und steuergeraet
DE69420444D1 (de) Antennenvorrichtung und Antennensystem
DE69315382D1 (de) Rechnersystem und Systemerweiterungseinheit
DE69326530D1 (de) Mehrrechnersystem
DE69428110D1 (de) Prozessor-system und fehlersuchmodus-durchfuehrungsverfahren
DE69315619T2 (de) Flammensperrendes und dunstabsorbierendes System
DE69301642T2 (de) Verbindungsstecker und Fixierungsplatte
DE69425752T2 (de) Kapazitiver detektor und alarmsystem
FI944064A (fi) Asennustuki ja asennusjärjestelmä
DE69333528D1 (de) D-n-carbamoylaminosaureamidohydrolase und hydantoinase
DE69804320D1 (de) Kraftabgängige detektoren und systemen
DE69518687D1 (de) Versorgung-unterscheidendes und Versorgung-adaptierendes elektronisches System
DE69523509T2 (de) Dezentralisiertes System und Mehrrechnersystem
FI932721A0 (fi) Ventilationssystem foer en roterande ugns utloppsgaser
DE69513913D1 (de) Sicherheitssystem und zugehöriger Detektor
GB2263348B (en) Microcomputer and card having the same
DE69619355T2 (de) Peripheriemodul und Mikroprozessorsystem
DE69119427D1 (de) Korrekturflüssigkeitssystem und verwendung desselben
ATE174744T1 (de) Automatisches rückrufsystem und betriebsverfahren
ATA96493A (de) Schwellen - hebe- und einbauvorrichtung
KR950007526U (ko) 마이크로컴퓨터를 이용한 전화기

Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HITACHI, LTD., TOKIO/TOKYO, JP HITACHI ULSI SYSTEM

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee