DE69326467T2 - Unterbrechungsfreies, wahlfreies zugriffspeichersystem. - Google Patents

Unterbrechungsfreies, wahlfreies zugriffspeichersystem.

Info

Publication number
DE69326467T2
DE69326467T2 DE69326467T DE69326467T DE69326467T2 DE 69326467 T2 DE69326467 T2 DE 69326467T2 DE 69326467 T DE69326467 T DE 69326467T DE 69326467 T DE69326467 T DE 69326467T DE 69326467 T2 DE69326467 T2 DE 69326467T2
Authority
DE
Germany
Prior art keywords
array
reprogramming
storage elements
configuration
disruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69326467T
Other languages
English (en)
Other versions
DE69326467D1 (de
Inventor
Rafael Camarota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Application granted granted Critical
Publication of DE69326467D1 publication Critical patent/DE69326467D1/de
Publication of DE69326467T2 publication Critical patent/DE69326467T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17752—Structural details of configuration resources for hot reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
DE69326467T 1992-07-02 1993-07-01 Unterbrechungsfreies, wahlfreies zugriffspeichersystem. Expired - Lifetime DE69326467T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US90770992A 1992-07-02 1992-07-02
PCT/US1993/006285 WO1994001867A1 (en) 1992-07-02 1993-07-01 Non-disruptive, randomly addressable memory system

Publications (2)

Publication Number Publication Date
DE69326467D1 DE69326467D1 (de) 1999-10-21
DE69326467T2 true DE69326467T2 (de) 2000-05-31

Family

ID=25424523

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69330974T Expired - Lifetime DE69330974T2 (de) 1992-07-02 1993-07-01 Unterbrechungsfreies wahlfreies Zugriffspeichersystem
DE69326467T Expired - Lifetime DE69326467T2 (de) 1992-07-02 1993-07-01 Unterbrechungsfreies, wahlfreies zugriffspeichersystem.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69330974T Expired - Lifetime DE69330974T2 (de) 1992-07-02 1993-07-01 Unterbrechungsfreies wahlfreies Zugriffspeichersystem

Country Status (8)

Country Link
US (2) US5488582A (de)
EP (2) EP0650631B1 (de)
JP (1) JPH07509800A (de)
KR (1) KR100320605B1 (de)
AT (2) ATE207234T1 (de)
DE (2) DE69330974T2 (de)
SG (1) SG49816A1 (de)
WO (1) WO1994001867A1 (de)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3168839B2 (ja) * 1994-09-09 2001-05-21 株式会社日立製作所 論理エミュレーションシステム及び等価回路生成方法
GB9508931D0 (en) * 1995-05-02 1995-06-21 Xilinx Inc Programmable switch for FPGA input/output signals
EP0769223B1 (de) * 1995-05-02 2003-10-15 Xilinx, Inc. Programmierbarer schalter für eingangs-/ausgangssignale eines anwenderprogrammierbaren gatterfeldes
US5646544A (en) * 1995-06-05 1997-07-08 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5764079A (en) * 1996-03-11 1998-06-09 Altera Corporation Sample and load scheme for observability of internal nodes in a PLD
US5821772A (en) * 1996-08-07 1998-10-13 Xilinx, Inc. Programmable address decoder for programmable logic device
US5838165A (en) * 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5946219A (en) * 1996-10-30 1999-08-31 Atmel Corporation Method and system for configuring an array of logic devices
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US6046603A (en) * 1997-12-12 2000-04-04 Xilinx, Inc. Method and apparatus for controlling the partial reconfiguration of a field programmable gate array
US6172520B1 (en) 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6028445A (en) * 1997-12-30 2000-02-22 Xilinx, Inc. Decoder structure and method for FPGA configuration
JPH11355961A (ja) * 1998-06-05 1999-12-24 Yazaki Corp Ｐｔｃ素子を有する回路保護装置及びｐｔｃ素子を有する回路保護装置を備えた電気接続箱
US6097210A (en) * 1998-08-04 2000-08-01 Xilinx, Inc. Multiplexer array with shifted input traces
US6069489A (en) * 1998-08-04 2000-05-30 Xilinx, Inc. FPGA having fast configuration memory data readback
US6137307A (en) 1998-08-04 2000-10-24 Xilinx, Inc. Structure and method for loading wide frames of data from a narrow input bus
US6305005B1 (en) 1999-01-14 2001-10-16 Xilinx, Inc. Methods to securely configure an FPGA using encrypted macros
US6301695B1 (en) 1999-01-14 2001-10-09 Xilinx, Inc. Methods to securely configure an FPGA using macro markers
US6324676B1 (en) 1999-01-14 2001-11-27 Xilinx, Inc. FPGA customizable to accept selected macros
US6160418A (en) * 1999-01-14 2000-12-12 Xilinx, Inc. Integrated circuit with selectively disabled logic blocks
US6357037B1 (en) 1999-01-14 2002-03-12 Xilinx, Inc. Methods to securely configure an FPGA to accept selected macros
US6654889B1 (en) 1999-02-19 2003-11-25 Xilinx, Inc. Method and apparatus for protecting proprietary configuration data for programmable logic devices
US6255848B1 (en) 1999-04-05 2001-07-03 Xilinx, Inc. Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA
US6262596B1 (en) 1999-04-05 2001-07-17 Xilinx, Inc. Configuration bus interface circuit for FPGAS
US6191614B1 (en) 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
JP2000311943A (ja) 1999-04-27 2000-11-07 Mitsubishi Electric Corp 半導体装置
JP2003505753A (ja) 1999-06-10 2003-02-12 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング セル構造におけるシーケンス分割方法
US6204687B1 (en) 1999-08-13 2001-03-20 Xilinx, Inc. Method and structure for configuring FPGAS
US7069320B1 (en) 1999-10-04 2006-06-27 International Business Machines Corporation Reconfiguring a network by utilizing a predetermined length quiescent state
AU1981400A (en) 1999-12-16 2001-06-25 Nokia Corporation High throughput and flexible device to secure data communication
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US7162644B1 (en) 2002-03-29 2007-01-09 Xilinx, Inc. Methods and circuits for protecting proprietary configuration data for programmable logic devices
US6996713B1 (en) 2002-03-29 2006-02-07 Xilinx, Inc. Method and apparatus for protecting proprietary decryption keys for programmable logic devices
EP1363132B1 (de) * 2002-05-13 2007-09-05 STMicroelectronics Pvt. Ltd Prüfverfahren und -gerät für Konfigurationsspeicherzellen in programmierbaren logischen Bauelementen (PLDS)
EP1537486A1 (de) 2002-09-06 2005-06-08 PACT XPP Technologies AG Rekonfigurierbare sequenzerstruktur
KR100597788B1 (ko) * 2004-12-17 2006-07-06 삼성전자주식회사 프로그램 동작 속도를 개선하는 불휘발성 반도체 메모리장치의 페이지 버퍼와 이에 대한 구동방법
US9231595B2 (en) * 2013-06-12 2016-01-05 International Business Machines Corporation Filtering event log entries
US11356404B2 (en) * 2020-03-04 2022-06-07 Qualcomm Incorporated Domain name system (DNS) override for edge computing

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE23950E (en) * 1946-12-23 1955-02-22 Method and means for chemical analysis
US3473160A (en) * 1966-10-10 1969-10-14 Stanford Research Inst Electronically controlled microelectronic cellular logic array
US3461435A (en) * 1966-11-04 1969-08-12 Burroughs Corp Pneumatic memory with electrical read-out means
US3531662A (en) * 1967-04-10 1970-09-29 Sperry Rand Corp Batch fabrication arrangement for integrated circuits
US4020469A (en) * 1975-04-09 1977-04-26 Frank Manning Programmable arrays
JPS6050940A (ja) * 1983-08-31 1985-03-22 Toshiba Corp 半導体集積回路
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4642487A (en) * 1984-09-26 1987-02-10 Xilinx, Inc. Special interconnect for configurable logic array
CA1269726A (en) * 1985-09-11 1990-05-29 Pilkington Micro-Electronics Limited Semi-conductor integrated circuits/systems
US4750155A (en) * 1985-09-19 1988-06-07 Xilinx, Incorporated 5-Transistor memory cell which can be reliably read and written
US4821233A (en) * 1985-09-19 1989-04-11 Xilinx, Incorporated 5-transistor memory cell with known state on power-up
US4791603A (en) * 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
US4918440A (en) * 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
JP2541248B2 (ja) * 1987-11-20 1996-10-09 三菱電機株式会社 プログラマブル・ロジック・アレイ
DE3886938T2 (de) * 1988-10-28 1994-06-30 Ibm Reprogrammierbare logische Sicherung für logische Anordnungen, basierend auf einer 6-Elementen-SRAM-Zelle.
US5193071A (en) * 1988-12-22 1993-03-09 Digital Equipment Corporation Memory apparatus for multiple processor systems
EP0388175B1 (de) * 1989-03-15 1995-11-02 Matsushita Electronics Corporation Halbleiter-Speichereinrichtung
US5343406A (en) * 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage
KR100248165B1 (ko) * 1992-04-16 2000-03-15 칼 하인쯔 호르닝어 여분구조를 가진 집적반도체메모리

Also Published As

Publication number Publication date
EP0877385A2 (de) 1998-11-11
ATE184728T1 (de) 1999-10-15
EP0877385A3 (de) 1999-03-03
DE69330974T2 (de) 2002-05-29
EP0877385B1 (de) 2001-10-17
KR100320605B1 (ko) 2002-04-22
JPH07509800A (ja) 1995-10-26
US5805503A (en) 1998-09-08
EP0650631A1 (de) 1995-05-03
KR950702736A (ko) 1995-07-29
ATE207234T1 (de) 2001-11-15
EP0650631B1 (de) 1999-09-15
DE69326467D1 (de) 1999-10-21
US5488582A (en) 1996-01-30
EP0650631A4 (de) 1995-12-13
DE69330974D1 (de) 2001-11-22
WO1994001867A1 (en) 1994-01-20
SG49816A1 (en) 1998-06-15

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Legal Events

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