DE69326986D1 - SIMD-Architektur mit einem Bus zur Datenübertragung von und zu Verarbeitungseinheiten - Google Patents
SIMD-Architektur mit einem Bus zur Datenübertragung von und zu VerarbeitungseinheitenInfo
- Publication number
- DE69326986D1 DE69326986D1 DE69326986T DE69326986T DE69326986D1 DE 69326986 D1 DE69326986 D1 DE 69326986D1 DE 69326986 T DE69326986 T DE 69326986T DE 69326986 T DE69326986 T DE 69326986T DE 69326986 D1 DE69326986 D1 DE 69326986D1
- Authority
- DE
- Germany
- Prior art keywords
- bus
- data transmission
- processing units
- simd architecture
- simd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/993,218 US5450603A (en) | 1992-12-18 | 1992-12-18 | SIMD architecture with transfer register or value source circuitry connected to bus |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69326986D1 true DE69326986D1 (de) | 1999-12-16 |
DE69326986T2 DE69326986T2 (de) | 2000-04-27 |
Family
ID=25539256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69326986T Expired - Fee Related DE69326986T2 (de) | 1992-12-18 | 1993-12-10 | SIMD-Architektur mit einem Bus zur Datenübertragung von und zu Verarbeitungseinheiten |
Country Status (4)
Country | Link |
---|---|
US (1) | US5450603A (de) |
EP (1) | EP0602909B1 (de) |
JP (1) | JPH06223209A (de) |
DE (1) | DE69326986T2 (de) |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
US5651121A (en) * | 1992-12-18 | 1997-07-22 | Xerox Corporation | Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand |
US5655131A (en) * | 1992-12-18 | 1997-08-05 | Xerox Corporation | SIMD architecture for connection to host processor's bus |
DE4344157A1 (de) * | 1993-12-23 | 1995-06-29 | Philips Patentverwaltung | Funkgerät |
US5557734A (en) * | 1994-06-17 | 1996-09-17 | Applied Intelligent Systems, Inc. | Cache burst architecture for parallel processing, such as for image processing |
US5659785A (en) * | 1995-02-10 | 1997-08-19 | International Business Machines Corporation | Array processor communication architecture with broadcast processor instructions |
US5754590A (en) * | 1996-05-17 | 1998-05-19 | Lucent Technologies, Inc. | Modem architecture for integrated controller and data pump applications |
US6551857B2 (en) | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
JPH1115773A (ja) * | 1997-06-24 | 1999-01-22 | Matsushita Electron Corp | 半導体集積回路、コンピュータシステム、データ処理装置及びデータ処理方法 |
JP4158864B2 (ja) | 1998-03-18 | 2008-10-01 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | マトリックスのコサイン変換を計算するためのデータ処理装置およびその方法 |
US6219733B1 (en) | 1998-08-26 | 2001-04-17 | International Business Machines Corporation | Transmission line loop |
US7627736B2 (en) | 1999-04-09 | 2009-12-01 | Clearspeed Technology Plc | Thread manager to control an array of processing elements |
GB2352306A (en) * | 1999-04-09 | 2001-01-24 | Pixelfusion Ltd | Parallel processing apparatus using a SIMD array |
US7526630B2 (en) | 1999-04-09 | 2009-04-28 | Clearspeed Technology, Plc | Parallel data processing apparatus |
US7506136B2 (en) | 1999-04-09 | 2009-03-17 | Clearspeed Technology Plc | Parallel data processing apparatus |
WO2001016702A1 (en) | 1999-09-01 | 2001-03-08 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
AU7099000A (en) | 1999-09-01 | 2001-03-26 | Intel Corporation | Branch instruction for processor |
JP3971535B2 (ja) * | 1999-09-10 | 2007-09-05 | 株式会社リコー | Simd型プロセッサ |
US7681018B2 (en) * | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US20020053017A1 (en) * | 2000-09-01 | 2002-05-02 | Adiletta Matthew J. | Register instructions for a multithreaded processor |
US7225281B2 (en) * | 2001-08-27 | 2007-05-29 | Intel Corporation | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
US7487505B2 (en) | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
US6868476B2 (en) | 2001-08-27 | 2005-03-15 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
US7216204B2 (en) | 2001-08-27 | 2007-05-08 | Intel Corporation | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
US7146391B2 (en) * | 2002-01-24 | 2006-12-05 | Broadcom Corporation | Method and system for implementing SLICE instructions |
US7610451B2 (en) | 2002-01-25 | 2009-10-27 | Intel Corporation | Data transfer mechanism using unidirectional pull bus and push bus |
US6803782B2 (en) * | 2002-03-21 | 2004-10-12 | John Conrad Koob | Arrayed processing element redundancy architecture |
US6806737B2 (en) * | 2002-03-21 | 2004-10-19 | Raymond Jit-Hung Sung | Bi-directional amplifier and method for accelerated bus line communication |
US7437724B2 (en) * | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
WO2004015764A2 (en) | 2002-08-08 | 2004-02-19 | Leedy Glenn J | Vertical system integration |
US7337275B2 (en) * | 2002-08-13 | 2008-02-26 | Intel Corporation | Free list and ring data structure management |
US7133563B2 (en) | 2002-10-31 | 2006-11-07 | Microsoft Corporation | Passive embedded interaction code |
US7116840B2 (en) | 2002-10-31 | 2006-10-03 | Microsoft Corporation | Decoding and error correction in 2-D arrays |
US6941438B2 (en) | 2003-01-10 | 2005-09-06 | Intel Corporation | Memory interleaving |
US7583842B2 (en) | 2004-01-06 | 2009-09-01 | Microsoft Corporation | Enhanced approach of m-array decoding and error correction |
US7263224B2 (en) | 2004-01-16 | 2007-08-28 | Microsoft Corporation | Strokes localization by m-array decoding and fast image matching |
US7607076B2 (en) | 2005-02-18 | 2009-10-20 | Microsoft Corporation | Embedded interaction code document |
US7826074B1 (en) | 2005-02-25 | 2010-11-02 | Microsoft Corporation | Fast embedded interaction code printing with custom postscript commands |
US7421439B2 (en) | 2005-04-22 | 2008-09-02 | Microsoft Corporation | Global metadata embedding and decoding |
US7599560B2 (en) | 2005-04-22 | 2009-10-06 | Microsoft Corporation | Embedded interaction code recognition |
US7542976B2 (en) * | 2005-04-22 | 2009-06-02 | Microsoft Corporation | Local metadata embedding and decoding |
US7400777B2 (en) | 2005-05-25 | 2008-07-15 | Microsoft Corporation | Preprocessing for information pattern analysis |
US7729539B2 (en) | 2005-05-31 | 2010-06-01 | Microsoft Corporation | Fast error-correcting of embedded interaction codes |
US7580576B2 (en) | 2005-06-02 | 2009-08-25 | Microsoft Corporation | Stroke localization and binding to electronic document |
US7619607B2 (en) | 2005-06-30 | 2009-11-17 | Microsoft Corporation | Embedding a pattern design onto a liquid crystal display |
US7817816B2 (en) | 2005-08-17 | 2010-10-19 | Microsoft Corporation | Embedded interaction code enabled surface type identification |
US7622182B2 (en) | 2005-08-17 | 2009-11-24 | Microsoft Corporation | Embedded interaction code enabled display |
JP4720436B2 (ja) * | 2005-11-01 | 2011-07-13 | 株式会社日立製作所 | リコンフィギュラブルプロセッサまたは装置 |
US7788468B1 (en) | 2005-12-15 | 2010-08-31 | Nvidia Corporation | Synchronization of threads in a cooperative thread array |
US7584342B1 (en) * | 2005-12-15 | 2009-09-01 | Nvidia Corporation | Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue |
US7861060B1 (en) * | 2005-12-15 | 2010-12-28 | Nvidia Corporation | Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior |
CN102508643A (zh) * | 2011-11-16 | 2012-06-20 | 刘大可 | 一种多核并行数字信号处理器及并行指令集的运行方法 |
US9262704B1 (en) * | 2015-03-04 | 2016-02-16 | Xerox Corporation | Rendering images to lower bits per pixel formats using reduced numbers of registers |
JP6627630B2 (ja) * | 2016-04-15 | 2020-01-08 | 富士通株式会社 | コンパイル方法、コンパイルプログラム及び情報処理装置 |
CN113867789A (zh) * | 2020-06-30 | 2021-12-31 | 上海寒武纪信息科技有限公司 | 计算装置、集成电路芯片、板卡、电子设备和计算方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4204251A (en) * | 1977-12-28 | 1980-05-20 | Finn Brudevold | Interconnection unit for multiple data processing systems |
JPS56164464A (en) * | 1980-05-21 | 1981-12-17 | Tatsuo Nogi | Parallel processing computer |
US4745546A (en) * | 1982-06-25 | 1988-05-17 | Hughes Aircraft Company | Column shorted and full array shorted functional plane for use in a modular array processor and method for using same |
WO1984004638A1 (en) * | 1983-05-12 | 1984-11-22 | American Telephone & Telegraph | Communication network |
US4814973A (en) * | 1983-05-31 | 1989-03-21 | Hillis W Daniel | Parallel processor |
JPH0642237B2 (ja) * | 1983-12-28 | 1994-06-01 | 株式会社日立製作所 | 並列処理装置 |
HU196230B (en) * | 1983-12-29 | 1988-10-28 | Chinoin Gyogyszer Es Vegyeszet | Process for producing water-soluble forms of polyene antibiotics and pharmaceutics comprising such active ingredient and plant protective with antifungal effect |
US4850027A (en) * | 1985-07-26 | 1989-07-18 | International Business Machines Corporation | Configurable parallel pipeline image processing system |
US4831519A (en) * | 1985-12-12 | 1989-05-16 | Itt Corporation | Cellular array processor with variable nesting depth vector control by selective enabling of left and right neighboring processor cells |
JPH0740252B2 (ja) * | 1986-03-08 | 1995-05-01 | 株式会社日立製作所 | マルチプロセツサシステム |
JPS63276659A (ja) * | 1987-03-27 | 1988-11-14 | Nec Corp | 複合コンピユ−タシステム |
US4984235A (en) * | 1987-04-27 | 1991-01-08 | Thinking Machines Corporation | Method and apparatus for routing message packets and recording the roofing sequence |
DE3851005T2 (de) * | 1987-06-01 | 1995-04-20 | Applied Intelligent Syst Inc | Paralleles Nachbarverarbeitungssystem und -Verfahren. |
US5129092A (en) * | 1987-06-01 | 1992-07-07 | Applied Intelligent Systems,Inc. | Linear chain of parallel processors and method of using same |
US5297255A (en) * | 1987-07-28 | 1994-03-22 | Hitachi, Ltd. | Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism |
US5113510A (en) * | 1987-12-22 | 1992-05-12 | Thinking Machines Corporation | Method and apparatus for operating a cache memory in a multi-processor |
US5148547A (en) * | 1988-04-08 | 1992-09-15 | Thinking Machines Corporation | Method and apparatus for interfacing bit-serial parallel processors to a coprocessor |
US5268856A (en) * | 1988-06-06 | 1993-12-07 | Applied Intelligent Systems, Inc. | Bit serial floating point parallel processing system and method |
US5280547A (en) * | 1990-06-08 | 1994-01-18 | Xerox Corporation | Dense aggregative hierarhical techniques for data analysis |
US5325500A (en) * | 1990-12-14 | 1994-06-28 | Xerox Corporation | Parallel processing units on a substrate, each including a column of memory |
US5148500A (en) * | 1991-01-24 | 1992-09-15 | Aoi Systems, Inc. | Morphological processing system |
-
1992
- 1992-12-18 US US07/993,218 patent/US5450603A/en not_active Expired - Fee Related
-
1993
- 1993-12-10 DE DE69326986T patent/DE69326986T2/de not_active Expired - Fee Related
- 1993-12-10 EP EP93309971A patent/EP0602909B1/de not_active Expired - Lifetime
- 1993-12-14 JP JP5313843A patent/JPH06223209A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US5450603A (en) | 1995-09-12 |
JPH06223209A (ja) | 1994-08-12 |
EP0602909A2 (de) | 1994-06-22 |
DE69326986T2 (de) | 2000-04-27 |
EP0602909B1 (de) | 1999-11-10 |
EP0602909A3 (de) | 1994-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69326986D1 (de) | SIMD-Architektur mit einem Bus zur Datenübertragung von und zu Verarbeitungseinheiten | |
DE69426447T2 (de) | Verfahren zur Durchführung von Bustransaktionen in einem Rechnersystem und Rechnersystem | |
DE69328320T2 (de) | Vorrichtung und Verfahren zur Datenübertragung zu und von einem Wirtrechnersystem | |
DE3887886D1 (de) | Verfahren und anordnung zur sicherung von angepasstem zugriff zu betriebsmitteln in einem multiprozessordatenverarbeitungssystem. | |
DE69433621D1 (de) | Geraet zur verarbeitung von befehlen in einem rechnersystem | |
DE69327243T2 (de) | System und verfahren zur dynamischen laufzeit-bindung von software-modulen in einem rechnersystem. | |
DE69424944D1 (de) | Datenreduktion in einem system zur analysierung von geometrischen datenbanken | |
EP0260409A3 (en) | Data processing system with two execution units | |
DE737370T1 (de) | Gerät zur übertragung von daten zu und von einer sich bewegenden vorrichtung | |
DE69632938D1 (de) | Verfahren und System zur sicheren Zugangskontrolle zu Systembetriebsmitteln in einem verteilten System | |
DE69031926D1 (de) | Instandhaltung von Dateiattributen in einem verteilten Datenverarbeitungssystem | |
DE3856030T2 (de) | Vorrichtung und Verfahren zur Durchführung von änderbarer Betriebsmittelaufteilung in einem Datenverarbeitungssystem mit zentralen Datenverarbeitungseinheiten mit verschiedenen Betriebssystemen | |
EP0523337A3 (en) | Self-scheduling parallel computer system and method | |
DE69320847T2 (de) | Verfahren und Anordnung zur Ausführung von Prozessen in einem Multiprozessor-System | |
DE69029438T2 (de) | Datenverarbeitungssystem mit Umwandlungsmittel von Burst-Operationen zu Pipeline-Operationen | |
DE69013394T2 (de) | Datenverarbeitungssystem mit Zweiwegarbiter zur Steuerung des Zugangs zu einem Systembus. | |
DE69323196T2 (de) | Rechnersystem und Verfahren zur Ausführung von mehreren Aufgaben | |
DE69330864T2 (de) | Verfahren zur Verwendung von Mehrfacheingabegriffeln in einem Mehrfachrechnersystem | |
DE69327150T2 (de) | Einzelbefehl- und Mehrfachdatenarchitektur (SIMD) zur Verbindung mit dem Bus eines Hauptprozessors | |
DE69228275T2 (de) | Umlegen von Leitungen in einem digitalen Übertragungssystem-SLC | |
DE69610874D1 (de) | Vorrichtung zur Datenübertragung zwischen einer Mehrzahl von Funktionsmodulen in einer lokalen Buseinheit und einem externen ARINC-629-Bus | |
BR8906579A (pt) | Sistema de processamento de dados tendo uma pluralidade de unidades de canalizacao conectadas em serie e processo de sua organizacao | |
DE3854859T2 (de) | Unterbrechungsabwicklung in einem parallelen Datenverarbeitungssystem | |
DE68928737D1 (de) | Vorrichtung zur handhabung von dokumenten in einem datenverarbeitungssystem | |
FI941288A0 (fi) | Tietokonejärjestelmiin liittyvä menetelmä ja järjestely |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |