DE69327288T2 - Verfahren und System zur Aufrechterhaltung der Adressenübersetzungspufferspeicher-Kohärenz eines Multiprozessorsystems - Google Patents

Verfahren und System zur Aufrechterhaltung der Adressenübersetzungspufferspeicher-Kohärenz eines Multiprozessorsystems

Info

Publication number
DE69327288T2
DE69327288T2 DE69327288T DE69327288T DE69327288T2 DE 69327288 T2 DE69327288 T2 DE 69327288T2 DE 69327288 T DE69327288 T DE 69327288T DE 69327288 T DE69327288 T DE 69327288T DE 69327288 T2 DE69327288 T2 DE 69327288T2
Authority
DE
Germany
Prior art keywords
address translation
cache coherency
translation cache
maintaining address
multiprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69327288T
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English (en)
Other versions
DE69327288D1 (de
Inventor
Charles Roberts Moore
John Stephen Muhich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69327288D1 publication Critical patent/DE69327288D1/de
Application granted granted Critical
Publication of DE69327288T2 publication Critical patent/DE69327288T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69327288T 1992-10-09 1993-09-20 Verfahren und System zur Aufrechterhaltung der Adressenübersetzungspufferspeicher-Kohärenz eines Multiprozessorsystems Expired - Fee Related DE69327288T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/959,189 US5437017A (en) 1992-10-09 1992-10-09 Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system

Publications (2)

Publication Number Publication Date
DE69327288D1 DE69327288D1 (de) 2000-01-20
DE69327288T2 true DE69327288T2 (de) 2000-06-08

Family

ID=25501759

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69327288T Expired - Fee Related DE69327288T2 (de) 1992-10-09 1993-09-20 Verfahren und System zur Aufrechterhaltung der Adressenübersetzungspufferspeicher-Kohärenz eines Multiprozessorsystems

Country Status (4)

Country Link
US (1) US5437017A (de)
EP (1) EP0592121B1 (de)
JP (1) JP2565648B2 (de)
DE (1) DE69327288T2 (de)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535351A (en) * 1994-04-04 1996-07-09 Motorola, Inc. Address translator with by-pass circuit and method of operation
US5530824A (en) * 1994-04-04 1996-06-25 Motorola, Inc. Address translation circuit
JP2625385B2 (ja) * 1994-06-30 1997-07-02 日本電気株式会社 マルチプロセッサシステム
US5630087A (en) * 1994-11-02 1997-05-13 Sun Microsystems, Inc. Apparatus and method for efficient sharing of virtual memory translations
US5829052A (en) * 1994-12-28 1998-10-27 Intel Corporation Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system
US5787476A (en) 1995-05-05 1998-07-28 Silicon Graphics, Inc. System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer
JP2842313B2 (ja) * 1995-07-13 1999-01-06 日本電気株式会社 情報処理装置
JP2830833B2 (ja) * 1996-04-30 1998-12-02 日本電気株式会社 プロセッサ間通信方法及びそれに用いるプロセッサ
US5944818A (en) * 1996-06-28 1999-08-31 Intel Corporation Method and apparatus for accelerated instruction restart in a microprocessor
US6199152B1 (en) 1996-08-22 2001-03-06 Transmeta Corporation Translated memory protection apparatus for an advanced microprocessor
US5906001A (en) * 1996-12-19 1999-05-18 Intel Corporation Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
US6490658B1 (en) * 1997-06-23 2002-12-03 Sun Microsystems, Inc. Data prefetch technique using prefetch cache, micro-TLB, and history file
WO1999008191A1 (en) * 1997-08-11 1999-02-18 Transmeta Corporation Translated memory protection apparatus for an advanced microprocessor
CN100392618C (zh) * 1997-08-11 2008-06-04 全斯美达有限公司 保护计算机内存储器被写入的系统、方法和设备
US6105113A (en) * 1997-08-21 2000-08-15 Silicon Graphics, Inc. System and method for maintaining translation look-aside buffer (TLB) consistency
US6021481A (en) * 1997-11-10 2000-02-01 International Business Machines Corporation Effective-to-real address cache managing apparatus and method
US6370632B1 (en) * 1997-11-18 2002-04-09 Intrinsity, Inc. Method and apparatus that enforces a regional memory model in hierarchical memory systems
US6119204A (en) * 1998-06-30 2000-09-12 International Business Machines Corporation Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization
JP2000067009A (ja) 1998-08-20 2000-03-03 Hitachi Ltd 主記憶共有型マルチプロセッサ
US6490671B1 (en) * 1999-05-28 2002-12-03 Oracle Corporation System for efficiently maintaining translation lockaside buffer consistency in a multi-threaded, multi-processor virtual memory system
US6363336B1 (en) * 1999-10-13 2002-03-26 Transmeta Corporation Fine grain translation discrimination
US7509391B1 (en) * 1999-11-23 2009-03-24 Texas Instruments Incorporated Unified memory management system for multi processor heterogeneous architecture
US6711671B1 (en) * 2000-02-18 2004-03-23 Hewlett-Packard Development Company, L.P. Non-speculative instruction fetch in speculative processing
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
US6604185B1 (en) * 2000-07-20 2003-08-05 Silicon Graphics, Inc. Distribution of address-translation-purge requests to multiple processors
US6931510B1 (en) * 2000-07-31 2005-08-16 Sun Microsystems, Inc. Method and system for translation lookaside buffer coherence in multiprocessor systems
US6779049B2 (en) * 2000-12-14 2004-08-17 International Business Machines Corporation Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
US6804741B2 (en) * 2002-01-16 2004-10-12 Hewlett-Packard Development Company, L.P. Coherent memory mapping tables for host I/O bridge
US7673304B2 (en) * 2003-02-18 2010-03-02 Microsoft Corporation Multithreaded kernel for graphics processing unit
US7073043B2 (en) * 2003-04-28 2006-07-04 International Business Machines Corporation Multiprocessor system supporting multiple outstanding TLBI operations per partition
US7617378B2 (en) * 2003-04-28 2009-11-10 International Business Machines Corporation Multiprocessor system with retry-less TLBI protocol
US7543291B2 (en) * 2003-08-01 2009-06-02 Hewlett-Packard Development Company, L.P. Processor purging system and method
US7735088B1 (en) 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US7503048B1 (en) 2003-08-18 2009-03-10 Cray Incorporated Scheduling synchronization of programs running as streams on multiple processors
US7421565B1 (en) * 2003-08-18 2008-09-02 Cray Inc. Method and apparatus for indirectly addressed vector load-add -store across multi-processors
US7069389B2 (en) * 2003-11-26 2006-06-27 Microsoft Corporation Lazy flushing of translation lookaside buffers
US20050273575A1 (en) * 2004-06-02 2005-12-08 Mukherjee Shubhendu S Mechanism to invalidate data translation buffer entries a multiprocessor system
US7281116B2 (en) * 2004-07-30 2007-10-09 Hewlett-Packard Development Company, L.P. Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes
US20060186119A1 (en) * 2005-02-23 2006-08-24 Yu Zheng Collapsible structures with liners
US7478769B1 (en) 2005-03-09 2009-01-20 Cray Inc. Method and apparatus for cooling electronic components
US7454590B2 (en) * 2005-09-09 2008-11-18 Sun Microsystems, Inc. Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores
US7383415B2 (en) * 2005-09-09 2008-06-03 Sun Microsystems, Inc. Hardware demapping of TLBs shared by multiple threads
US7739476B2 (en) * 2005-11-04 2010-06-15 Apple Inc. R and C bit update handling
US7788464B2 (en) * 2006-12-22 2010-08-31 Microsoft Corporation Scalability of virtual TLBs for multi-processor virtual machines
US8112174B2 (en) * 2008-02-25 2012-02-07 International Business Machines Corporation Processor, method and computer program product for fast selective invalidation of translation lookaside buffer
US8412911B2 (en) * 2009-06-29 2013-04-02 Oracle America, Inc. System and method to invalidate obsolete address translations
WO2012070291A1 (ja) * 2010-11-26 2012-05-31 インターナショナル・ビジネス・マシーンズ・コーポレーション キャッシュコヒーレンシ制御の方法、システムおよびプログラム
US8595464B2 (en) 2011-07-14 2013-11-26 Oracle International Corporation Dynamic sizing of translation lookaside buffer for power reduction
US9665505B2 (en) 2014-11-14 2017-05-30 Cavium, Inc. Managing buffered communication between sockets
US9870328B2 (en) * 2014-11-14 2018-01-16 Cavium, Inc. Managing buffered communication between cores
US9697137B2 (en) * 2014-11-14 2017-07-04 Cavium, Inc. Filtering translation lookaside buffer invalidations
US9684606B2 (en) * 2014-11-14 2017-06-20 Cavium, Inc. Translation lookaside buffer invalidation suppression
US20160378812A1 (en) * 2015-06-25 2016-12-29 International Business Machines Corporation Reduction of bind breaks
US10318430B2 (en) * 2015-06-26 2019-06-11 International Business Machines Corporation System operation queue for transaction
US9898416B2 (en) 2015-12-22 2018-02-20 International Business Machines Corporation Translation entry invalidation in a multithreaded data processing system
US9830198B2 (en) 2015-12-22 2017-11-28 International Business Machines Corporation Translation entry invalidation in a multithreaded data processing system
US9575815B1 (en) 2015-12-22 2017-02-21 International Business Machines Corporation Translation entry invalidation in a multithreaded data processing system
US9715459B2 (en) 2015-12-22 2017-07-25 International Business Machines Corporation Translation entry invalidation in a multithreaded data processing system
US9928119B2 (en) 2015-12-22 2018-03-27 International Business Machines Corporation Translation entry invalidation in a multithreaded data processing system
US9779028B1 (en) 2016-04-01 2017-10-03 Cavium, Inc. Managing translation invalidation
US20190087217A1 (en) * 2017-09-19 2019-03-21 Microsoft Technology Licensing, Llc Hypervisor memory cache invalidation
US10754790B2 (en) 2018-04-26 2020-08-25 Qualcomm Incorporated Translation of virtual addresses to physical addresses using translation lookaside buffer information
US11327759B2 (en) * 2018-09-25 2022-05-10 Marvell Asia Pte, Ltd. Managing low-level instructions and core interactions in multi-core processors
US10740239B2 (en) 2018-12-11 2020-08-11 International Business Machines Corporation Translation entry invalidation in a multithreaded data processing system
US10977183B2 (en) 2018-12-11 2021-04-13 International Business Machines Corporation Processing a sequence of translation entry invalidation requests with regard to draining a processor core
US10817434B2 (en) 2018-12-19 2020-10-27 International Business Machines Corporation Interruptible translation entry invalidation in a multithreaded data processing system
US11537519B1 (en) 2021-07-29 2022-12-27 International Business Machines Corporation Marking in-flight requests affected by translation entry invalidation in a data processing system

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254346A (ja) * 1984-05-31 1985-12-16 Toshiba Corp マルチプロセツサシステム
JPS63201854A (ja) * 1987-02-18 1988-08-19 Hitachi Ltd アドレス変換バツフア無効化方式
JPH01109452A (ja) * 1987-10-22 1989-04-26 Fujitsu Ltd 変換索引バッファ情報の消去制御方式
US5283886A (en) * 1989-08-11 1994-02-01 Hitachi, Ltd. Multiprocessor cache system having three states for generating invalidating signals upon write accesses
US5113514A (en) * 1989-08-22 1992-05-12 Prime Computer, Inc. System bus for multiprocessor computer system
US5197139A (en) * 1990-04-05 1993-03-23 International Business Machines Corporation Cache management for multi-processor systems utilizing bulk cross-invalidate
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
CA2045756C (en) * 1990-06-29 1996-08-20 Gregg Bouchard Combined queue for invalidates and return data in multiprocessor system
US5303362A (en) * 1991-03-20 1994-04-12 Digital Equipment Corporation Coupled memory multiprocessor computer system including cache coherency management protocols

Also Published As

Publication number Publication date
JP2565648B2 (ja) 1996-12-18
US5437017A (en) 1995-07-25
JPH06187241A (ja) 1994-07-08
EP0592121A1 (de) 1994-04-13
DE69327288D1 (de) 2000-01-20
EP0592121B1 (de) 1999-12-15

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee