DE69328432D1 - Taktrückgewinnungsschaltung für synchrone wellenformabtastung - Google Patents

Taktrückgewinnungsschaltung für synchrone wellenformabtastung

Info

Publication number
DE69328432D1
DE69328432D1 DE69328432T DE69328432T DE69328432D1 DE 69328432 D1 DE69328432 D1 DE 69328432D1 DE 69328432 T DE69328432 T DE 69328432T DE 69328432 T DE69328432 T DE 69328432T DE 69328432 D1 DE69328432 D1 DE 69328432D1
Authority
DE
Germany
Prior art keywords
recovery circuit
clock recovery
synchronous waveform
waveform scan
scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69328432T
Other languages
English (en)
Other versions
DE69328432T2 (de
Inventor
T Behrens
Trent Dudley
Neal Glover
R Welland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Application granted granted Critical
Publication of DE69328432D1 publication Critical patent/DE69328432D1/de
Publication of DE69328432T2 publication Critical patent/DE69328432T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/005—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which one of the oscillations is, or is converted into, a signal having a special waveform, e.g. triangular
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation
DE69328432T 1992-09-30 1993-09-24 Taktrückgewinnungsschaltung für synchrone wellenformabtastung Expired - Lifetime DE69328432T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/954,350 US5359631A (en) 1992-09-30 1992-09-30 Timing recovery circuit for synchronous waveform sampling
PCT/US1993/009110 WO1994008394A1 (en) 1992-09-30 1993-09-24 Timing recovery circuit for synchronous waveform sampling

Publications (2)

Publication Number Publication Date
DE69328432D1 true DE69328432D1 (de) 2000-05-25
DE69328432T2 DE69328432T2 (de) 2000-09-14

Family

ID=25495302

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69328432T Expired - Lifetime DE69328432T2 (de) 1992-09-30 1993-09-24 Taktrückgewinnungsschaltung für synchrone wellenformabtastung

Country Status (6)

Country Link
US (1) US5359631A (de)
EP (1) EP0663117B1 (de)
JP (1) JP2952042B2 (de)
DE (1) DE69328432T2 (de)
SG (1) SG46437A1 (de)
WO (1) WO1994008394A1 (de)

Families Citing this family (40)

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US5424881A (en) * 1993-02-01 1995-06-13 Cirrus Logic, Inc. Synchronous read channel
US6452736B1 (en) * 1994-05-26 2002-09-17 Hitachi, Ltd. Magnetic recording and reproducing apparatus and a read/write amplifier having a signal transmission system with high speed of data write signal
US5576904A (en) * 1994-09-27 1996-11-19 Cirrus Logic, Inc. Timing gradient smoothing circuit in a synchronous read channel
US5668678B1 (en) * 1994-11-14 2000-11-28 Cirrus Logic Inc Detecting servo data and servo bursts from discrete time samples of an analog read signal in a sampled amplitude read channel
US5585975A (en) * 1994-11-17 1996-12-17 Cirrus Logic, Inc. Equalization for sample value estimation and sequence detection in a sampled amplitude read channel
US5572558A (en) * 1994-11-17 1996-11-05 Cirrus Logic, Inc. PID loop filter for timing recovery in a sampled amplitude read channel
US5504790A (en) * 1994-12-09 1996-04-02 Conner Peripherals, Inc. Digital data phase detector
EP0806040A1 (de) 1994-12-09 1997-11-12 Seagate Technology, Inc. Vorrichtung und verfahren zur steuerung der frequenz mit welcher daten in einemplattenlaufwerksystem geschrieben werden
US5696639A (en) * 1995-05-12 1997-12-09 Cirrus Logic, Inc. Sampled amplitude read channel employing interpolated timing recovery
US5793548A (en) * 1995-05-12 1998-08-11 Cirrus Logic, Inc. Fault tolerant sync mark detector for comparing a sign and magnitude of a detected sequence to a target sync mark in sampled amplitude magnetic recording
US5796535A (en) * 1995-05-12 1998-08-18 Cirrus Logic, Inc. Sampled amplitude read channel employing a user data frequency synthesizer and a servo data frequency synthesizer
US6002274A (en) * 1995-09-29 1999-12-14 Dallas Semiconductor Oversampled state machine for jitter tolerant pulse detection
US5760984A (en) * 1995-10-20 1998-06-02 Cirrus Logic, Inc. Cost reduced interpolated timing recovery in a sampled amplitude read channel
US5717619A (en) * 1995-10-20 1998-02-10 Cirrus Logic, Inc. Cost reduced time varying fir filter
US5726818A (en) 1995-12-05 1998-03-10 Cirrus Logic, Inc. Magnetic disk sampled amplitude read channel employing interpolated timing recovery for synchronous detection of embedded servo data
US5812336A (en) * 1995-12-05 1998-09-22 Cirrus Logic, Inc. Fixed sample rate sampled amplitude read channel for zoned magnetic recording
US5999355A (en) 1996-04-30 1999-12-07 Cirrus Logic, Inc. Gain and phase constrained adaptive equalizing filter in a sampled amplitude read channel for magnetic recording
US6819514B1 (en) 1996-04-30 2004-11-16 Cirrus Logic, Inc. Adaptive equalization and interpolated timing recovery in a sampled amplitude read channel for magnetic recording
US5786950A (en) * 1996-07-29 1998-07-28 Cirrus Logic, Inc. PR4 sampled amplitude read channel employing an NRZI write modulator and a PR4/NRZI converter
US5802118A (en) * 1996-07-29 1998-09-01 Cirrus Logic, Inc. Sub-sampled discrete time read channel for computer storage systems
US5838738A (en) * 1996-07-29 1998-11-17 Cirrus Logic, Inc. Coding to improve timing recovery in a sampled amplitude read channel
US5949820A (en) * 1996-08-01 1999-09-07 Nec Electronics Inc. Method for optimizing an equalization and receive filter
US5808573A (en) * 1996-08-01 1998-09-15 Nec Electronics Incorporated Methods and structure for sampled-data timing recovery with reduced complexity and latency
US5914989A (en) * 1997-02-19 1999-06-22 Nec Electronics, Inc. PRML system with reduced complexity maximum likelihood detector
US6032284A (en) * 1997-03-12 2000-02-29 Cirrus Logic, Inc. Trellis coding system for disc storage systems
US6324225B1 (en) * 1997-12-22 2001-11-27 Stmicroelectronics, Inc. Timing recovery for data sampling of a detector
FR2775143B1 (fr) * 1998-02-18 2000-05-05 Atg Sa Procede de correction automatique du gain d'une boucle d'asservissement, en particulier d'asservissement de phase d'une horloge de lecture d'un lecteur-enregistreur de disque optique numerique et dispositif associe
US6246723B1 (en) 1998-05-04 2001-06-12 Cirrus Logic, Inc. Sampled amplitude read channel employing early-decisions from a trellis sequence detector for sampling value estimation
US6823133B1 (en) 1999-11-15 2004-11-23 Lexmark International, Inc. Apparatus and method for electronic control of DC motor using an all-digital phase-locked loop
US6775084B1 (en) 2000-02-14 2004-08-10 Stmicroelectronics, Inc. Circuit and method for determining the phase difference between a sample clock and a sampled signal
US7519137B2 (en) * 2001-08-02 2009-04-14 Agere Systems, Inc. Timing recovery in data communication circuits
KR100468162B1 (ko) * 2001-08-10 2005-01-26 삼성전자주식회사 비대칭에러 보정장치 및 그 방법과, 이를 적용한 광학재생 시스템의 클럭복원장치
AU2003216690A1 (en) * 2002-04-23 2003-11-10 Koninklijke Philips Electronics N.V. Interference-free lms-based adaptive asynchronous receiver
US7102839B2 (en) * 2003-10-31 2006-09-05 International Business Machines Corporation Magnetic recording channel utilizing control fields for timing recovery, equalization, amplitude and amplitude asymmetry
US7920601B2 (en) 2003-12-19 2011-04-05 Gentex Corporation Vehicular communications system having improved serial communication
WO2005062815A2 (en) * 2003-12-19 2005-07-14 Gentex Corporation Device with improved serial communication
US7123429B2 (en) * 2004-02-26 2006-10-17 Hitachi Global Storage Technologies Netherlands B.V. Method and apparatus for providing write pre-compensation using a read timing path
US7002764B2 (en) 2004-02-26 2006-02-21 Hitachi Global Storage Technologies Netherlands B.V. Method and apparatus for providing generalized write pre-compensation
US7433142B2 (en) * 2006-02-01 2008-10-07 International Business Machines Corporation Using at least one servo channel to provide timing recovery and timing information to data channels
CN111010169B (zh) 2018-10-08 2024-01-19 中兴通讯股份有限公司 相位检测方法、装置、存储介质及电子装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4416017A (en) * 1981-01-05 1983-11-15 Motorola, Inc. Apparatus and method for attenuating interfering signals
US4609907A (en) * 1984-10-31 1986-09-02 International Business Machines Corporation Dual channel partial response system
DE3778549D1 (de) * 1987-11-13 1992-05-27 Ibm Schnelle takterfassung fuer partial-response-signalisierung.
US5068628A (en) * 1990-11-13 1991-11-26 Level One Communications, Inc. Digitally controlled timing recovery loop
US5216554A (en) * 1991-07-01 1993-06-01 International Business Machines Corporation Digital phase error estimator
JP2978621B2 (ja) * 1992-02-18 1999-11-15 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路

Also Published As

Publication number Publication date
WO1994008394A1 (en) 1994-04-14
JP2952042B2 (ja) 1999-09-20
EP0663117A4 (de) 1995-11-02
EP0663117A1 (de) 1995-07-19
DE69328432T2 (de) 2000-09-14
EP0663117B1 (de) 2000-04-19
US5359631A (en) 1994-10-25
SG46437A1 (en) 1998-02-20
JPH08502393A (ja) 1996-03-12

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