DE69329778D1 - System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor - Google Patents

System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor

Info

Publication number
DE69329778D1
DE69329778D1 DE69329778T DE69329778T DE69329778D1 DE 69329778 D1 DE69329778 D1 DE 69329778D1 DE 69329778 T DE69329778 T DE 69329778T DE 69329778 T DE69329778 T DE 69329778T DE 69329778 D1 DE69329778 D1 DE 69329778D1
Authority
DE
Germany
Prior art keywords
super
stores
handling loads
scalar microprocessor
scalar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69329778T
Other languages
English (en)
Other versions
DE69329778T2 (de
Inventor
Cheryl Senter
Johannes Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of DE69329778D1 publication Critical patent/DE69329778D1/de
Application granted granted Critical
Publication of DE69329778T2 publication Critical patent/DE69329778T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61K—PREPARATIONS FOR MEDICAL, DENTAL OR TOILETRY PURPOSES
    • A61K47/00—Medicinal preparations characterised by the non-active ingredients used, e.g. carriers or inert additives; Targeting or modifying agents chemically bound to the active ingredient
    • A61K47/30—Macromolecular organic or inorganic compounds, e.g. inorganic polyphosphates
    • A61K47/32—Macromolecular compounds obtained by reactions only involving carbon-to-carbon unsaturated bonds, e.g. carbomers, poly(meth)acrylates, or polyvinyl pyrrolidone
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
DE69329778T 1992-09-29 1993-09-03 System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor Expired - Lifetime DE69329778T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US95408492A 1992-09-29 1992-09-29
PCT/US1993/008331 WO1994008287A1 (en) 1992-09-29 1993-09-03 System and method for handling load and/or store operations in a superscalar microprocessor

Publications (2)

Publication Number Publication Date
DE69329778D1 true DE69329778D1 (de) 2001-01-25
DE69329778T2 DE69329778T2 (de) 2001-04-26

Family

ID=25494898

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69329778T Expired - Lifetime DE69329778T2 (de) 1992-09-29 1993-09-03 System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor

Country Status (7)

Country Link
US (5) US5659782A (de)
EP (1) EP0663083B1 (de)
JP (28) JP3644959B2 (de)
KR (1) KR100248903B1 (de)
DE (1) DE69329778T2 (de)
HK (1) HK1014780A1 (de)
WO (1) WO1994008287A1 (de)

Families Citing this family (161)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4237417C2 (de) * 1992-03-25 1997-01-30 Hewlett Packard Co Datenverarbeitungssystem
KR100248903B1 (ko) 1992-09-29 2000-03-15 야스카와 히데아키 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5721857A (en) * 1993-12-30 1998-02-24 Intel Corporation Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor
US6378062B1 (en) * 1994-01-04 2002-04-23 Intel Corporation Method and apparatus for performing a store operation
US5717882A (en) * 1994-01-04 1998-02-10 Intel Corporation Method and apparatus for dispatching and executing a load operation to memory
US5694574A (en) * 1994-01-04 1997-12-02 Intel Corporation Method and apparatus for performing load operations in a computer system
US6021471A (en) * 1994-11-15 2000-02-01 Advanced Micro Devices, Inc. Multiple level cache control system with address and data pipelines
US5734874A (en) * 1994-04-29 1998-03-31 Sun Microsystems, Inc. Central processing unit with integrated graphics functions
US6279099B1 (en) * 1994-04-29 2001-08-21 Sun Microsystems, Inc. Central processing unit with integrated graphics functions
JP3164732B2 (ja) 1994-07-04 2001-05-08 富士通株式会社 データ処理装置
US5761475A (en) * 1994-12-15 1998-06-02 Sun Microsystems, Inc. Computer processor having a register file with reduced read and/or write port bandwidth
US5784586A (en) * 1995-02-14 1998-07-21 Fujitsu Limited Addressing method for executing load instructions out of order with respect to store instructions
US5745729A (en) * 1995-02-16 1998-04-28 Sun Microsystems, Inc. Methods and apparatuses for servicing load instructions
US5638312A (en) * 1995-03-03 1997-06-10 Hal Computer Systems, Inc. Method and apparatus for generating a zero bit status flag in a microprocessor
TW448403B (en) * 1995-03-03 2001-08-01 Matsushita Electric Ind Co Ltd Pipeline data processing device and method for executing multiple data processing data dependent relationship
US5802588A (en) * 1995-04-12 1998-09-01 Advanced Micro Devices, Inc. Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non-blocking fashion from a load/store buffer
US5887152A (en) * 1995-04-12 1999-03-23 Advanced Micro Devices, Inc. Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions
US5625835A (en) * 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
US5761712A (en) * 1995-06-07 1998-06-02 Advanced Micro Devices Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
US5778434A (en) 1995-06-07 1998-07-07 Seiko Epson Corporation System and method for processing multiple requests and out of order returns
US5694565A (en) * 1995-09-11 1997-12-02 International Business Machines Corporation Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions
US5745724A (en) * 1996-01-26 1998-04-28 Advanced Micro Devices, Inc. Scan chain for rapidly identifying first or second objects of selected types in a sequential list
US5754812A (en) * 1995-10-06 1998-05-19 Advanced Micro Devices, Inc. Out-of-order load/store execution control
US6038657A (en) * 1995-10-06 2000-03-14 Advanced Micro Devices, Inc. Scan chains for out-of-order load/store execution control
US5835747A (en) * 1996-01-26 1998-11-10 Advanced Micro Devices, Inc. Hierarchical scan logic for out-of-order load/store execution control
EP0853787B1 (de) * 1995-10-06 2003-07-02 Advanced Micro Devices, Inc. Abtastkette zur schnellen feststellung eines ersten und zweiten objektes von ausgewählten typen in einer sequentiellen liste
US5764943A (en) * 1995-12-28 1998-06-09 Intel Corporation Data path circuitry for processor having multiple instruction pipelines
US6092184A (en) * 1995-12-28 2000-07-18 Intel Corporation Parallel processing of pipelined instructions having register dependencies
US5781790A (en) * 1995-12-29 1998-07-14 Intel Corporation Method and apparatus for performing floating point to integer transfers and vice versa
US5778210A (en) * 1996-01-11 1998-07-07 Intel Corporation Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
US5751946A (en) * 1996-01-18 1998-05-12 International Business Machines Corporation Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor
US5930489A (en) * 1996-02-09 1999-07-27 Advanced Micro Devices, Inc. Microprocessor configured to detect memory operations having data addresses indicative of a boundary between instructions sets
US5809275A (en) * 1996-03-01 1998-09-15 Hewlett-Packard Company Store-to-load hazard resolution system and method for a processor that executes instructions out of order
US5838942A (en) * 1996-03-01 1998-11-17 Hewlett-Packard Company Panic trap system and method
US5813033A (en) * 1996-03-08 1998-09-22 Advanced Micro Devices, Inc. Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and another cache
US5968166A (en) * 1996-03-22 1999-10-19 Matsushita Electric Industrial Co., Ltd. Information processing apparatus and method, and scheduling device for reducing inactivity due to wait state
US5737749A (en) * 1996-05-20 1998-04-07 International Business Machines Corporation Method and system for dynamically sharing cache capacity in a microprocessor
US5860158A (en) * 1996-11-15 1999-01-12 Samsung Electronics Company, Ltd. Cache control unit with a cache request transaction-oriented protocol
US5890207A (en) * 1996-11-27 1999-03-30 Emc Corporation High performance integrated cached storage device
US5890219A (en) * 1996-11-27 1999-03-30 Emc Corporation Redundant writing of data to cached storage system
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource
US5897666A (en) * 1996-12-09 1999-04-27 International Business Machines Corporation Generation of unique address alias for memory disambiguation buffer to avoid false collisions
US5841998A (en) * 1996-12-31 1998-11-24 Metaflow Technologies, Inc. System and method of processing instructions for a processor
US6230245B1 (en) 1997-02-11 2001-05-08 Micron Technology, Inc. Method and apparatus for generating a variable sequence of memory device command signals
US6175894B1 (en) 1997-03-05 2001-01-16 Micron Technology, Inc. Memory device command buffer apparatus and method and memory devices and computer systems using same
US5931957A (en) * 1997-03-31 1999-08-03 International Business Machines Corporation Support for out-of-order execution of loads and stores in a processor
US6021485A (en) * 1997-04-10 2000-02-01 International Business Machines Corporation Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
US5987574A (en) * 1997-04-30 1999-11-16 Sony Corporation Bank arbitration for SDRAM memory control
US5996043A (en) 1997-06-13 1999-11-30 Micron Technology, Inc. Two step memory device command buffer apparatus and method and memory devices and computer systems using same
US6484244B1 (en) 1997-06-17 2002-11-19 Micron Technology, Inc. Method and system for storing and processing multiple memory commands
US6058472A (en) * 1997-06-25 2000-05-02 Sun Microsystems, Inc. Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine
US6085289A (en) * 1997-07-18 2000-07-04 International Business Machines Corporation Method and system for load data formatting and improved method for cache line organization
US6070238A (en) * 1997-09-11 2000-05-30 International Business Machines Corporation Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction
US6112293A (en) * 1997-11-17 2000-08-29 Advanced Micro Devices, Inc. Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result
US6202119B1 (en) 1997-12-19 2001-03-13 Micron Technology, Inc. Method and system for processing pipelined memory commands
US6112297A (en) * 1998-02-10 2000-08-29 International Business Machines Corporation Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution
US6360314B1 (en) * 1998-07-14 2002-03-19 Compaq Information Technologies Group, L.P. Data cache having store queue bypass for out-of-order instruction execution and method for same
US6175905B1 (en) * 1998-07-30 2001-01-16 Micron Technology, Inc. Method and system for bypassing pipelines in a pipelined memory command generator
US7779236B1 (en) * 1998-12-31 2010-08-17 Stmicroelectronics, Inc. Symbolic store-load bypass
US8065504B2 (en) 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US6978462B1 (en) * 1999-01-28 2005-12-20 Ati International Srl Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US6336183B1 (en) * 1999-02-26 2002-01-01 International Business Machines Corporation System and method for executing store instructions
US6237066B1 (en) * 1999-03-22 2001-05-22 Sun Microsystems, Inc. Supporting multiple outstanding requests to multiple targets in a pipelined memory system
US6393536B1 (en) 1999-05-18 2002-05-21 Advanced Micro Devices, Inc. Load/store unit employing last-in-buffer indication for rapid load-hit-store
US6473837B1 (en) 1999-05-18 2002-10-29 Advanced Micro Devices, Inc. Snoop resynchronization mechanism to preserve read ordering
US6427193B1 (en) 1999-05-18 2002-07-30 Advanced Micro Devices, Inc. Deadlock avoidance using exponential backoff
US6266744B1 (en) * 1999-05-18 2001-07-24 Advanced Micro Devices, Inc. Store to load forwarding using a dependency link file
US6415360B1 (en) 1999-05-18 2002-07-02 Advanced Micro Devices, Inc. Minimizing self-modifying code checks for uncacheable memory types
US6473832B1 (en) 1999-05-18 2002-10-29 Advanced Micro Devices, Inc. Load/store unit having pre-cache and post-cache queues for low latency load memory operations
US7089404B1 (en) 1999-06-14 2006-08-08 Transmeta Corporation Method and apparatus for enhancing scheduling in an advanced microprocessor
US6134646A (en) * 1999-07-29 2000-10-17 International Business Machines Corp. System and method for executing and completing store instructions
US6915385B1 (en) * 1999-07-30 2005-07-05 International Business Machines Corporation Apparatus for unaligned cache reads and methods therefor
US6549959B1 (en) 1999-08-30 2003-04-15 Ati International Srl Detecting modification to computer memory by a DMA device
US6662280B1 (en) 1999-11-10 2003-12-09 Advanced Micro Devices, Inc. Store buffer which forwards data based on index and optional way match
US6539467B1 (en) * 1999-11-15 2003-03-25 Texas Instruments Incorporated Microprocessor with non-aligned memory access
US6970996B1 (en) * 2000-01-04 2005-11-29 National Semiconductor Corporation Operand queue for use in a floating point unit to reduce read-after-write latency and method of operation
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
DE10121792C2 (de) * 2000-05-26 2003-09-25 Ibm Universelle Ladeadresse/Wertevorhersageschema
US6848024B1 (en) 2000-08-07 2005-01-25 Broadcom Corporation Programmably disabling one or more cache entries
US6732234B1 (en) 2000-08-07 2004-05-04 Broadcom Corporation Direct access mode for a cache
US6748492B1 (en) * 2000-08-07 2004-06-08 Broadcom Corporation Deterministic setting of replacement policy in a cache through way selection
JP4025493B2 (ja) * 2000-08-08 2007-12-19 富士通株式会社 適切な発行先に命令を発行する命令発行装置
US7757066B2 (en) 2000-12-29 2010-07-13 Stmicroelectronics, Inc. System and method for executing variable latency load operations in a date processor
JP3776732B2 (ja) * 2001-02-02 2006-05-17 株式会社東芝 プロセッサ装置
FR2821449B1 (fr) * 2001-02-27 2003-07-04 St Microelectronics Sa Procede de gestion d'instructions au sein d'un processeur a architecture decouplee, en particulier un processeur de traitement numerique du signal, et processeur correspondant
US6748495B2 (en) 2001-05-15 2004-06-08 Broadcom Corporation Random generator
US6959348B1 (en) * 2001-07-30 2005-10-25 Vixs Systems, Inc. Method and system for accessing data
US20030065909A1 (en) * 2001-09-28 2003-04-03 Jourdan Stephan J. Deferral of dependent loads until after execution of colliding stores
US7529912B2 (en) * 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7181596B2 (en) 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7315921B2 (en) * 2002-02-19 2008-01-01 Ip-First, Llc Apparatus and method for selective memory attribute control
US7328328B2 (en) 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7395412B2 (en) * 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7546446B2 (en) * 2002-03-08 2009-06-09 Ip-First, Llc Selective interrupt suppression
US6804759B2 (en) * 2002-03-14 2004-10-12 International Business Machines Corporation Method and apparatus for detecting pipeline address conflict using compare of byte addresses
US6963964B2 (en) 2002-03-14 2005-11-08 International Business Machines Corporation Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7380103B2 (en) 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
US7373483B2 (en) 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
US7185180B2 (en) * 2002-04-02 2007-02-27 Ip-First, Llc Apparatus and method for selective control of condition code write back
US7380109B2 (en) * 2002-04-15 2008-05-27 Ip-First, Llc Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US7181598B2 (en) * 2002-05-17 2007-02-20 Intel Corporation Prediction of load-store dependencies in a processing agent
US7218647B2 (en) * 2002-06-27 2007-05-15 International Business Machines Corporation Method and apparatus for implementing frame header alterations
JP3808013B2 (ja) * 2002-07-05 2006-08-09 富士通株式会社 命令実行装置
US7062636B2 (en) * 2002-09-19 2006-06-13 Intel Corporation Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation
US7145567B2 (en) * 2003-04-03 2006-12-05 Avid Technology, Inc. Bitstream format and reading and writing methods and apparatus therefor
US7321964B2 (en) * 2003-07-08 2008-01-22 Advanced Micro Devices, Inc. Store-to-load forwarding buffer using indexed lookup
US6925928B2 (en) * 2003-09-18 2005-08-09 Anthony Fox Trash compactor for fast food restaurant waste
US7721069B2 (en) * 2004-07-13 2010-05-18 3Plus1 Technology, Inc Low power, high performance, heterogeneous, scalable processor architecture
US7376817B2 (en) * 2005-08-10 2008-05-20 P.A. Semi, Inc. Partial load/store forward prediction
US7644258B2 (en) * 2005-08-29 2010-01-05 Searete, Llc Hybrid branch predictor using component predictors each having confidence and override signals
US8296550B2 (en) * 2005-08-29 2012-10-23 The Invention Science Fund I, Llc Hierarchical register file with operand capture ports
US9176741B2 (en) * 2005-08-29 2015-11-03 Invention Science Fund I, Llc Method and apparatus for segmented sequential storage
US8275976B2 (en) * 2005-08-29 2012-09-25 The Invention Science Fund I, Llc Hierarchical instruction scheduler facilitating instruction replay
US20070083735A1 (en) * 2005-08-29 2007-04-12 Glew Andrew F Hierarchical processor
US7461239B2 (en) * 2006-02-02 2008-12-02 International Business Machines Corporation Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
CN101288055B (zh) * 2006-11-07 2010-10-13 日立软件工程株式会社 数据处理控制方法，信息处理设备和数据处理控制系统
JP5145929B2 (ja) * 2007-03-08 2013-02-20 株式会社リコー 半導体集積回路及び画像処理装置
US7600099B2 (en) * 2007-03-08 2009-10-06 International Business Machines Corporation System and method for predictive early allocation of stores in a microprocessor
US20090006712A1 (en) * 2007-06-29 2009-01-01 Fatma Ehsan Data ordering in a multi-node system
JP5315748B2 (ja) * 2008-03-28 2013-10-16 富士通株式会社 マイクロプロセッサおよびシグネチャ生成方法ならびに多重化システムおよび多重化実行検証方法
JP5206385B2 (ja) * 2008-12-12 2013-06-12 日本電気株式会社 バウンダリ実行制御システム、バウンダリ実行制御方法、及びバウンダリ実行制御プログラム
US8266411B2 (en) * 2009-02-05 2012-09-11 International Business Machines Corporation Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance
US7895381B2 (en) * 2009-02-16 2011-02-22 Himax Media Solutions, Inc. Data accessing system
GB2469299B (en) * 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
US8078796B2 (en) * 2009-04-14 2011-12-13 Micron Technology, Inc. Method for writing to and erasing a non-volatile memory
US8392666B2 (en) * 2009-05-21 2013-03-05 Via Technologies, Inc. Low power high speed load-store collision detector
US8977819B2 (en) * 2010-09-21 2015-03-10 Texas Instruments Incorporated Prefetch stream filter with FIFO allocation and stream direction prediction
EP2440016B1 (de) * 2010-10-08 2019-01-23 Lantiq Beteiligungs-GmbH & Co.KG Laserdiodensteuervorrichtung
US9128725B2 (en) 2012-05-04 2015-09-08 Apple Inc. Load-store dependency predictor content management
US9600289B2 (en) 2012-05-30 2017-03-21 Apple Inc. Load-store dependency predictor PC hashing
JP6344022B2 (ja) * 2014-04-08 2018-06-20 富士通株式会社 演算処理装置および演算処理装置の制御方法
US9710268B2 (en) 2014-04-29 2017-07-18 Apple Inc. Reducing latency for pointer chasing loads
US11561792B2 (en) * 2015-06-08 2023-01-24 Qualcomm Incorporated System, apparatus, and method for a transient load instruction within a VLIW operation
US10241800B2 (en) 2015-06-16 2019-03-26 International Business Machines Corporation Split-level history buffer in a computer processing unit
US10503506B2 (en) * 2015-10-19 2019-12-10 Arm Limited Apparatus and method for accessing data in a cache in response to an unaligned load instruction
US10191748B2 (en) * 2015-11-30 2019-01-29 Intel IP Corporation Instruction and logic for in-order handling in an out-of-order processor
DE102015224300A1 (de) * 2015-12-04 2017-06-08 Siemens Aktiengesellschaft Speicherprogrammierbarer Baustein und Verfahren zur geschützten Übertragung von Daten auf einen speicherprogrammierbaren Baustein
US10514925B1 (en) 2016-01-28 2019-12-24 Apple Inc. Load speculation recovery
US10437595B1 (en) 2016-03-15 2019-10-08 Apple Inc. Load/store dependency predictor optimization for replayed loads
US11048506B2 (en) 2016-08-19 2021-06-29 Advanced Micro Devices, Inc. Tracking stores and loads by bypassing load store units
US10331357B2 (en) * 2016-08-19 2019-06-25 Advanced Micro Devices, Inc. Tracking stores and loads by bypassing load store units
US10353707B2 (en) 2017-07-12 2019-07-16 International Business Machines Corporation Efficient pointer load and format
US11175924B2 (en) 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US10572256B2 (en) 2017-10-06 2020-02-25 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10606590B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Effective address based load store unit in out of order processors
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port
US10579387B2 (en) 2017-10-06 2020-03-03 International Business Machines Corporation Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor
EP3825848A1 (de) * 2019-04-04 2021-05-26 Cambricon Technologies Corporation Limited Datenverarbeitungsverfahren und -vorrichtung und zugehöriges produkt

Family Cites Families (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3346851A (en) 1964-07-08 1967-10-10 Control Data Corp Simultaneous multiprocessing computer system
US3541528A (en) * 1969-01-06 1970-11-17 Ibm Implicit load and store mechanism
US3789365A (en) 1971-06-03 1974-01-29 Bunker Ramo Processor interrupt system
US3771138A (en) 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
US3916388A (en) 1974-05-30 1975-10-28 Ibm Shifting apparatus for automatic data alignment
US4084235A (en) 1975-04-14 1978-04-11 Honeywell Information Systems Inc. Emulation apparatus
US4034349A (en) 1976-01-29 1977-07-05 Sperry Rand Corporation Apparatus for processing interrupts in microprocessing systems
AU529675B2 (en) 1977-12-07 1983-06-16 Honeywell Information Systems Incorp. Cache memory unit
US4315314A (en) 1977-12-30 1982-02-09 Rca Corporation Priority vectored interrupt having means to supply branch address directly
US4200927A (en) 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4189772A (en) 1978-03-16 1980-02-19 International Business Machines Corporation Operand alignment controls for VFL instructions
US4189768A (en) 1978-03-16 1980-02-19 International Business Machines Corporation Operand fetch control improvement
US4236206A (en) 1978-10-25 1980-11-25 Digital Equipment Corporation Central processor unit for executing instructions of variable length
US4228495A (en) 1978-12-19 1980-10-14 Allen-Bradley Company Multiprocessor numerical control system
JPS6041768B2 (ja) 1979-01-19 1985-09-18 株式会社日立製作所 デ−タ処理装置
US4296470A (en) 1979-06-21 1981-10-20 International Business Machines Corp. Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt system
JPS5616248A (en) 1979-07-17 1981-02-17 Matsushita Electric Ind Co Ltd Processing system for interruption
JPS5847053B2 (ja) * 1979-11-19 1983-10-20 株式会社日立製作所 デ−タ処理装置
CA1174370A (en) 1980-05-19 1984-09-11 Hidekazu Matsumoto Data processing unit with pipelined operands
JPS5743239A (en) 1980-08-27 1982-03-11 Hitachi Ltd Data processor
JPS6028015B2 (ja) 1980-08-28 1985-07-02 日本電気株式会社 情報処理装置
US4434461A (en) 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
JPS5757345A (en) 1980-09-24 1982-04-06 Toshiba Corp Data controller
US4654781A (en) 1981-10-02 1987-03-31 Raytheon Company Byte addressable memory for variable length instructions and data
JPS58151655A (ja) 1982-03-03 1983-09-08 Fujitsu Ltd 情報処理装置
US4514803A (en) 1982-04-26 1985-04-30 International Business Machines Corporation Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof
JPS58217054A (ja) * 1982-06-11 1983-12-16 Hitachi Ltd デ−タ処理装置
JPS5932045A (ja) 1982-08-16 1984-02-21 Hitachi Ltd 情報処理装置
JPS59501684A (ja) 1982-10-22 1984-10-04 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン 目的命令ストリ−ムへ殆んど実時間で插入するためのソ−スおよび目的命令ストリ−ムの外部における加速式命令写像
JPS59154548A (ja) * 1983-02-22 1984-09-03 Hitachi Ltd 記憶制御方式
JPS59165143A (ja) * 1983-03-11 1984-09-18 Hitachi Ltd デ−タ処理装置
US4569016A (en) 1983-06-30 1986-02-04 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
US4800486A (en) 1983-09-29 1989-01-24 Tandem Computers Incorporated Multiple data patch CPU architecture
US4807115A (en) 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
GB8329509D0 (en) 1983-11-04 1983-12-07 Inmos Ltd Computer
JPH063584B2 (ja) * 1983-12-19 1994-01-12 株式会社日立製作所 情報処理装置
JPS60225943A (ja) 1984-04-25 1985-11-11 Hitachi Ltd 例外割込み処理方式
US4720779A (en) 1984-06-28 1988-01-19 Burroughs Corporation Stored logic program scanner for a data processor having internal plural data and instruction streams
JPS6133546A (ja) * 1984-07-25 1986-02-17 Nec Corp 情報処理装置
US4766564A (en) 1984-08-13 1988-08-23 International Business Machines Corporation Dual putaway/bypass busses for multiple arithmetic units
US4739472A (en) * 1984-12-07 1988-04-19 Nec Corporation Information processing device capable of rapidly processing instructions of different groups
US5025368A (en) 1984-12-27 1991-06-18 Sony Corporation Microprocessor with option area adjacent CPU core facilitating interfacing with peripheral devices
US4794517A (en) 1985-04-15 1988-12-27 International Business Machines Corporation Three phased pipelined signal processor
US4679141A (en) * 1985-04-29 1987-07-07 International Business Machines Corporation Pageable branch history table
US4714994A (en) 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
JPH0762823B2 (ja) 1985-05-22 1995-07-05 株式会社日立製作所 デ−タ処理装置
EP0205193B1 (de) * 1985-06-17 1996-10-23 Nec Corporation Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers
US4739471A (en) 1985-06-28 1988-04-19 Hewlett-Packard Company Method and means for moving bytes in a reduced instruction set computer
US4734852A (en) * 1985-08-30 1988-03-29 Advanced Micro Devices, Inc. Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
US4722049A (en) * 1985-10-11 1988-01-26 Unisys Corporation Apparatus for out-of-order program execution
JPS62152043A (ja) 1985-12-26 1987-07-07 Nec Corp 命令コ−ドアクセス制御方式
JPS62165242A (ja) 1986-01-17 1987-07-21 Toshiba Corp プロセツサ
DE3603240A1 (de) * 1986-02-03 1987-08-06 Siemens Ag Schaltungsanordnung zur bereinigung von operandenkonflikten in nach dem fliessbandprinzip arbeitenden datenverarbeitungsanlagen
DE3751503T2 (de) 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
US4903196A (en) 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US5051940A (en) * 1990-04-04 1991-09-24 International Business Machines Corporation Data dependency collapsing hardware apparatus
JPS6324428A (ja) 1986-07-17 1988-02-01 Mitsubishi Electric Corp キヤツシユメモリ
US4766566A (en) 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
CA1286784C (en) * 1986-08-27 1991-07-23 Joseph A. Petolino, Jr. Cache storage queue
US5133072A (en) 1986-11-13 1992-07-21 Hewlett-Packard Company Method for improved code generation in reduced instruction set computers
JPS63131230A (ja) 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置
US4992934A (en) 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
EP0272198A3 (de) * 1986-12-15 1991-10-16 United Technologies Corporation Rechenvorrichtung und -verfahren mit eingeschränktem Befehlssatz
US4814976C1 (en) * 1986-12-23 2002-06-04 Mips Tech Inc Risc computer with unaligned reference handling and method for the same
JPS63163930A (ja) 1986-12-26 1988-07-07 Toshiba Corp アライメント補正方式
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
US4992938A (en) 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
US5134561A (en) 1987-07-20 1992-07-28 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
US4901233A (en) 1987-07-20 1990-02-13 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
US4942520A (en) * 1987-07-31 1990-07-17 Prime Computer, Inc. Method and apparatus for indexing, accessing and updating a memory
US4916652A (en) 1987-09-30 1990-04-10 International Business Machines Corporation Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures
EP0312764A3 (de) * 1987-10-19 1991-04-10 International Business Machines Corporation Datenprozessor mit mehrfachen Ausführungseinheiten zur parallelen Ausführung von mehreren Befehlsklassen
US5247628A (en) * 1987-11-30 1993-09-21 International Business Machines Corporation Parallel processor instruction dispatch apparatus with interrupt handler
JP2667849B2 (ja) * 1988-01-06 1997-10-27 株式会社日立製作所 情報処理装置
US4926323A (en) 1988-03-03 1990-05-15 Advanced Micro Devices, Inc. Streamlined instruction processor
JPH01286030A (ja) * 1988-05-12 1989-11-17 Nec Corp 情報処理装置
US5003462A (en) 1988-05-31 1991-03-26 International Business Machines Corporation Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means
US4897810A (en) 1988-06-13 1990-01-30 Advanced Micro Devices, Inc. Asynchronous interrupt status bit circuit
EP0348628A3 (de) 1988-06-28 1991-01-02 International Business Machines Corporation Cache-Speicheranordnung
US5148536A (en) * 1988-07-25 1992-09-15 Digital Equipment Corporation Pipeline having an integral cache which processes cache misses and loads data in parallel
JPH0673105B2 (ja) 1988-08-11 1994-09-14 株式会社東芝 命令パイプライン方式のマイクロプロセッサ
US5101341A (en) 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
JP2810068B2 (ja) 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
JPH0760408B2 (ja) * 1988-11-30 1995-06-28 松下電器産業株式会社 データ処理装置
JPH02151930A (ja) * 1988-12-05 1990-06-11 Nec Corp ストアバツフア管理方式
GB8828817D0 (en) 1988-12-09 1989-01-18 Int Computers Ltd Data processing apparatus
US4961162A (en) * 1989-01-13 1990-10-02 International Business Machines Corporation Multiprocessing system for performing floating point arithmetic operations
US5127091A (en) 1989-01-13 1992-06-30 International Business Machines Corporation System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
US5075840A (en) 1989-01-13 1991-12-24 International Business Machines Corporation Tightly coupled multiprocessor instruction synchronization
WO1990008355A1 (en) 1989-01-17 1990-07-26 Fujitsu Limited Microprocessor
US5148528A (en) 1989-02-03 1992-09-15 Digital Equipment Corporation Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length
US5113515A (en) 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
US4985825A (en) 1989-02-03 1991-01-15 Digital Equipment Corporation System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer
US5226126A (en) 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5768575A (en) 1989-02-24 1998-06-16 Advanced Micro Devices, Inc. Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
GB2230116B (en) 1989-04-07 1993-02-17 Intel Corp An improvement for pipelined decoding of instructions in a pipelined processor
CA2016068C (en) 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
JPH0314025A (ja) 1989-06-13 1991-01-22 Nec Corp 命令実行制御方式
EP0419105B1 (de) 1989-09-21 1997-08-13 Texas Instruments Incorporated Integrierte Schaltung, die an der Oberfläche eines Halbleitersubstrats angeordnet ist, und Verfahren zur Herstellung derselben
JP2835103B2 (ja) 1989-11-01 1998-12-14 富士通株式会社 命令指定方法及び命令実行方式
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5185871A (en) * 1989-12-26 1993-02-09 International Business Machines Corporation Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
US5193206A (en) 1989-12-27 1993-03-09 Motorola, Inc. Reduce instruction set microprocessor
US5185868A (en) * 1990-01-16 1993-02-09 Advanced Micro Devices, Inc. Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy
US5251306A (en) * 1990-01-16 1993-10-05 Advanced Micro Devices, Inc. Apparatus for controlling execution of a program in a computing device
US5168571A (en) 1990-01-24 1992-12-01 International Business Machines Corporation System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data
US5230068A (en) 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
GB2241801B (en) * 1990-03-05 1994-03-16 Intel Corp Data bypass structure in a register file on a microprocessor chip to ensure data integrity
CA2038264C (en) 1990-06-26 1995-06-27 Richard James Eickemeyer In-memory preprocessor for a scalable compound instruction set machine processor
US5155843A (en) * 1990-06-29 1992-10-13 Digital Equipment Corporation Error transition mode for multi-processor system
US5193167A (en) * 1990-06-29 1993-03-09 Digital Equipment Corporation Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system
JP2834289B2 (ja) * 1990-07-20 1998-12-09 株式会社日立製作所 マイクロプロセッサ
US5163139A (en) 1990-08-29 1992-11-10 Hitachi America, Ltd. Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
EP0479390B1 (de) 1990-10-05 1999-01-07 Koninklijke Philips Electronics N.V. Verarbeitungsgerät mit Speicherschaltung und eine Gruppe von Funktionseinheiten
JP2532300B2 (ja) 1990-10-17 1996-09-11 三菱電機株式会社 並列処理装置における命令供給装置
US5317740A (en) * 1991-03-07 1994-05-31 Digital Equipment Corporation Alternate and iterative analysis of computer programs for locating translatable code by resolving callbacks and other conflicting mutual dependencies
US5261071A (en) 1991-03-21 1993-11-09 Control Data System, Inc. Dual pipe cache memory with out-of-order issue capability
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5345569A (en) 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
US5323489A (en) * 1991-11-14 1994-06-21 Bird Peter L Method and apparatus employing lookahead to reduce memory bank contention for decoupled operand references
US5371684A (en) * 1992-03-31 1994-12-06 Seiko Epson Corporation Semiconductor floor plan for a register renaming circuit
US5418973A (en) 1992-06-22 1995-05-23 Digital Equipment Corporation Digital computer system with cache controller coordinating both vector and scalar operations
US5442756A (en) 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor
US5619668A (en) 1992-08-10 1997-04-08 Intel Corporation Apparatus for register bypassing in a microprocessor
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
KR100248903B1 (ko) * 1992-09-29 2000-03-15 야스카와 히데아키 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템
EP0651321B1 (de) 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5574927A (en) * 1994-03-25 1996-11-12 International Meta Systems, Inc. RISC architecture computer configured for emulation of the instruction set of a target computer
US5778210A (en) * 1996-01-11 1998-07-07 Intel Corporation Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
US5832205A (en) * 1996-08-20 1998-11-03 Transmeta Corporation Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed

Also Published As

Publication number Publication date
JP2005025788A (ja) 2005-01-27
JP2005166046A (ja) 2005-06-23
JP3852475B2 (ja) 2006-11-29
JP2003177913A (ja) 2003-06-27
EP0663083A1 (de) 1995-07-19
JP2000148494A (ja) 2000-05-30
US5987593A (en) 1999-11-16
JP3772901B2 (ja) 2006-05-10
JP2005243050A (ja) 2005-09-08
JP2000148481A (ja) 2000-05-30
JP3772902B2 (ja) 2006-05-10
JP2000148480A (ja) 2000-05-30
JP2000148491A (ja) 2000-05-30
WO1994008287A1 (en) 1994-04-14
JP3852474B2 (ja) 2006-11-29
JP2005174364A (ja) 2005-06-30
JP3772899B2 (ja) 2006-05-10
JP3644959B2 (ja) 2005-05-11
JP3588755B2 (ja) 2004-11-17
JP2000148490A (ja) 2000-05-30
JP3772905B2 (ja) 2006-05-10
JP2000181708A (ja) 2000-06-30
JP3874022B2 (ja) 2007-01-31
JP3772903B2 (ja) 2006-05-10
US5557763A (en) 1996-09-17
JP2005235233A (ja) 2005-09-02
JP2006277776A (ja) 2006-10-12
US7000097B2 (en) 2006-02-14
JP2005353091A (ja) 2005-12-22
JP2000148493A (ja) 2000-05-30
DE69329778T2 (de) 2001-04-26
JP2005322269A (ja) 2005-11-17
JP3772907B2 (ja) 2006-05-10
KR100248903B1 (ko) 2000-03-15
JP2005149525A (ja) 2005-06-09
JP2005141780A (ja) 2005-06-02
JP3620530B2 (ja) 2005-02-16
JP3815507B2 (ja) 2006-08-30
JP2003131872A (ja) 2003-05-09
US5659782A (en) 1997-08-19
JP2005216326A (ja) 2005-08-11
JP3741146B2 (ja) 2006-02-01
JP2006073025A (ja) 2006-03-16
US20030056089A1 (en) 2003-03-20
JP2006048713A (ja) 2006-02-16
JPH08504977A (ja) 1996-05-28
JP3741144B2 (ja) 2006-02-01
HK1014780A1 (en) 1999-09-30
JP3627737B2 (ja) 2005-03-09
EP0663083B1 (de) 2000-12-20
JP3741149B2 (ja) 2006-02-01
JP3772900B2 (ja) 2006-05-10
JP2000148483A (ja) 2000-05-30
JP2003131870A (ja) 2003-05-09
JP2005050371A (ja) 2005-02-24
US6434693B1 (en) 2002-08-13
KR950703325A (ko) 1995-09-20
JP2003131871A (ja) 2003-05-09
JP2000148492A (ja) 2000-05-30

Similar Documents

Publication Publication Date Title
DE69329778D1 (de) System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor
DE69320847D1 (de) Verfahren und Anordnung zur Ausführung von Prozessen in einem Multiprozessor-System
DE69301342T2 (de) Verfahren und Vorrichtung zur Handhabung von trägerbandlosen Etiketten
DE69426447D1 (de) Verfahren zur Durchführung von Bustransaktionen in einem Rechnersystem und Rechnersystem
DE69531497D1 (de) Verfahren zur spaltenbildung in und stützung von lagerstätten
DE69229755T2 (de) Anordnung und Verfahren zur Freigabe von geschützten Prozessen in einem verteilten Mehrprozessdatensystem
DE69320297T2 (de) Verfahren und Vorrichtung zur Messung von Betriebszuständen in einem Lager
DE69129526D1 (de) Multiprozessorsystem und Verfahren zur Überwachung der Ausführung von Tasks in einem Multiprozesorsystem
DE69500424D1 (de) Verfahren und gerät zur sicheren objektveränderung in einem verteilten system
DE69414988T2 (de) Verfahren und Vorrichtung zur Handhabung von Folien
DE69308957D1 (de) Verfahren und Vorrichtung zur Handhabung von Proben
DE69331956D1 (de) Verfahren und System zur Feststellung einer Flüssigkeit in einem Gehäuse
DE69308032D1 (de) Verfahren und system zum verbinden von objekten in einem rechnersystem
DE69028637D1 (de) Vorrichtung und verfahren zur lagerung und zum transport von müll
DE69229997D1 (de) Gerät und verfahren zur sortierung von gegenständen
DE69322944T2 (de) Handhabungssystem und Verfahren für flache Gegenstände in Einzelbehältern
DE69325339D1 (de) Verfahren und Vorrichtung zur Unterscheidung von Artikeln wie Briefumschläge
DE69323196T2 (de) Rechnersystem und Verfahren zur Ausführung von mehreren Aufgaben
DE59302807D1 (de) Einrichtung und verfahren zur handhabung von gegenständen
DE69418082D1 (de) System und Verfahren zur Vermeidung von Verklemmung in einem Rechner
DE69421991T2 (de) Flasche aus Polyester und Verfahren zur Entfernung von sich auf der Flasche befindenden Stoffe
DE69326705D1 (de) Verfahren und Anordnung zur Feststellung der Befehlsablauffolge in einem Datenverarbeitungssystem
DE69327924D1 (de) Verfahren zur automatischen Initialisierung eines Mikroprozessorsystems und entsprechendes System
DE59405948D1 (de) Verfahren zur Erstellung und/oder Änderung von NC-Programmen
DE69313966T2 (de) Verfahren und Vorrichtung zur Abtrennung von NOx und/oder SOx

Legal Events

Date Code Title Description
8364 No opposition during term of opposition