DE69332619D1 - Verfahren zur Herstellung von einem Feldeffektbauelement mit einem isolierten Gatter - Google Patents

Verfahren zur Herstellung von einem Feldeffektbauelement mit einem isolierten Gatter

Info

Publication number
DE69332619D1
DE69332619D1 DE69332619T DE69332619T DE69332619D1 DE 69332619 D1 DE69332619 D1 DE 69332619D1 DE 69332619 T DE69332619 T DE 69332619T DE 69332619 T DE69332619 T DE 69332619T DE 69332619 D1 DE69332619 D1 DE 69332619D1
Authority
DE
Germany
Prior art keywords
manufacturing
field effect
effect device
insulated gate
insulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69332619T
Other languages
English (en)
Other versions
DE69332619T2 (de
Inventor
Keith Michael Hutchings
Andrew Leonard Goodyear
Andrew Mark Warwick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Philips Electronics UK Ltd
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics UK Ltd, Koninklijke Philips Electronics NV filed Critical Philips Electronics UK Ltd
Application granted granted Critical
Publication of DE69332619D1 publication Critical patent/DE69332619D1/de
Publication of DE69332619T2 publication Critical patent/DE69332619T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/126—Power FETs
DE69332619T 1992-07-23 1993-07-20 Verfahren zur Herstellung von einem Feldeffektbauelement mit einem isolierten Gatter Expired - Fee Related DE69332619T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB929215653A GB9215653D0 (en) 1992-07-23 1992-07-23 A method of manufacturing a semiconductor device comprising an insulated gate field effect device

Publications (2)

Publication Number Publication Date
DE69332619D1 true DE69332619D1 (de) 2003-02-13
DE69332619T2 DE69332619T2 (de) 2003-08-21

Family

ID=10719168

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69332619T Expired - Fee Related DE69332619T2 (de) 1992-07-23 1993-07-20 Verfahren zur Herstellung von einem Feldeffektbauelement mit einem isolierten Gatter

Country Status (5)

Country Link
US (1) US5387528A (de)
EP (1) EP0583022B1 (de)
JP (1) JP3413248B2 (de)
DE (1) DE69332619T2 (de)
GB (1) GB9215653D0 (de)

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US5558313A (en) * 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
US5910669A (en) * 1992-07-24 1999-06-08 Siliconix Incorporated Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof
GB9216599D0 (en) * 1992-08-05 1992-09-16 Philips Electronics Uk Ltd A semiconductor device comprising a vertical insulated gate field effect device and a method of manufacturing such a device
JP3396553B2 (ja) * 1994-02-04 2003-04-14 三菱電機株式会社 半導体装置の製造方法及び半導体装置
JP3307785B2 (ja) * 1994-12-13 2002-07-24 三菱電機株式会社 絶縁ゲート型半導体装置
US6008520A (en) * 1994-12-30 1999-12-28 Siliconix Incorporated Trench MOSFET with heavily doped delta layer to provide low on- resistance
US5674766A (en) * 1994-12-30 1997-10-07 Siliconix Incorporated Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer
US5688725A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance
US5567634A (en) * 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
US6140678A (en) * 1995-06-02 2000-10-31 Siliconix Incorporated Trench-gated power MOSFET with protective diode
US6049108A (en) * 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
US5998837A (en) * 1995-06-02 1999-12-07 Siliconix Incorporated Trench-gated power MOSFET with protective diode having adjustable breakdown voltage
US5856692A (en) * 1995-06-02 1999-01-05 Siliconix Incorporated Voltage-clamped power accumulation-mode MOSFET
EP0746042B1 (de) * 1995-06-02 2004-03-31 SILICONIX Incorporated Bidirektional sperrender Graben-Leistungs-MOSFET
EP0746030B1 (de) * 1995-06-02 2001-11-21 SILICONIX Incorporated Grabengate-Leistungs-MOSFET mit Schutzdioden in periodischer Anordnung
JP3384198B2 (ja) * 1995-07-21 2003-03-10 三菱電機株式会社 絶縁ゲート型半導体装置およびその製造方法
US5689128A (en) * 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor
US5949124A (en) * 1995-10-31 1999-09-07 Motorola, Inc. Edge termination structure
KR100223198B1 (ko) * 1996-04-11 1999-10-15 다니구찌 이찌로오, 기타오카 다카시 높은 강복 전압을 갖는 반도체 장치 및 그 제조 방법
US6046078A (en) * 1997-04-28 2000-04-04 Megamos Corp. Semiconductor device fabrication with reduced masking steps
US6096608A (en) * 1997-06-30 2000-08-01 Siliconix Incorporated Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench
US6097061A (en) * 1998-03-30 2000-08-01 Advanced Micro Devices, Inc. Trenched gate metal oxide semiconductor device and method
TW389988B (en) * 1998-05-22 2000-05-11 United Microelectronics Corp Method for forming metal interconnect in dielectric layer with low dielectric constant
US6204128B1 (en) * 1998-10-26 2001-03-20 Matsushita Electronics Corporation Method for fabricating semiconductor device
US6316299B1 (en) * 1999-03-04 2001-11-13 United Microelectronics Corp. Formation of laterally diffused metal-oxide semiconductor device
GB9906247D0 (en) 1999-03-18 1999-05-12 Koninkl Philips Electronics Nv An electronic device comprising a trench gate field effect device
GB9907184D0 (en) 1999-03-30 1999-05-26 Philips Electronics Nv A method of manufacturing a semiconductor device
JP4244456B2 (ja) * 1999-08-04 2009-03-25 株式会社デンソー 半導体装置の製造方法、絶縁ゲート型バイポーラトランジスタの製造方法及び絶縁ゲート型バイポーラトランジスタ
EP1127379B1 (de) * 1999-08-19 2010-06-02 Infineon Technologies AG Vertikal aufgebautes leistungshalbleiterbauelement
JP4932088B2 (ja) 2001-02-19 2012-05-16 ルネサスエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP3939195B2 (ja) 2002-05-13 2007-07-04 ローム株式会社 半導体装置の製造方法および半導体装置
US6852634B2 (en) * 2002-06-27 2005-02-08 Semiconductor Components Industries L.L.C. Low cost method of providing a semiconductor device having a high channel density
JP5008046B2 (ja) 2005-06-14 2012-08-22 ローム株式会社 半導体デバイス
US9437729B2 (en) 2007-01-08 2016-09-06 Vishay-Siliconix High-density power MOSFET with planarized metalization
US9947770B2 (en) 2007-04-03 2018-04-17 Vishay-Siliconix Self-aligned trench MOSFET and method of manufacture
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
JP5166940B2 (ja) * 2008-03-31 2013-03-21 シリコニックス・インコーポレイテッド 側壁スペーサを用いる高密度トレンチ形ｄｍｏｓの製造
US9443974B2 (en) 2009-08-27 2016-09-13 Vishay-Siliconix Super junction trench power MOSFET device fabrication
US9431530B2 (en) 2009-10-20 2016-08-30 Vishay-Siliconix Super-high density trench MOSFET
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9722041B2 (en) 2012-09-19 2017-08-01 Vishay-Siliconix Breakdown voltage blocking device
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
EP3183753A4 (de) 2014-08-19 2018-01-10 Vishay-Siliconix Elektronische schaltung
US9704858B2 (en) * 2015-07-09 2017-07-11 O2Micro, Inc. Integrated device having multiple transistors

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4374455A (en) * 1979-10-30 1983-02-22 Rca Corporation Method for manufacturing a vertical, grooved MOSFET
JPS5912028B2 (ja) * 1981-08-31 1984-03-19 株式会社日立製作所 半導体装置の製造法
US4983535A (en) * 1981-10-15 1991-01-08 Siliconix Incorporated Vertical DMOS transistor fabrication process
GB2131603B (en) * 1982-12-03 1985-12-18 Philips Electronic Associated Semiconductor devices
DE3245457A1 (de) * 1982-12-08 1984-06-14 Siemens AG, 1000 Berlin und 8000 München Halbleiterelement mit kontaktloch
GB2134705B (en) * 1983-01-28 1985-12-24 Philips Electronic Associated Semiconductor devices
DE3402867A1 (de) * 1984-01-27 1985-08-01 Siemens AG, 1000 Berlin und 8000 München Halbleiterbauelement mit kontaktloch
US4830981A (en) * 1984-07-03 1989-05-16 Texas Instruments Inc. Trench capacitor process for high density dynamic ram
GB2167229B (en) * 1984-11-21 1988-07-20 Philips Electronic Associated Semiconductor devices
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device
EP0255970B1 (de) * 1986-08-08 1993-12-15 Philips Electronics Uk Limited Verfahren zur Herstellung eines Feldeffekttransistors mit isoliertem Gate
US5160491A (en) * 1986-10-21 1992-11-03 Texas Instruments Incorporated Method of making a vertical MOS transistor
US4914058A (en) * 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
JPH0290567A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 半導体装置とその製造方法
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5242845A (en) * 1990-06-13 1993-09-07 Kabushiki Kaisha Toshiba Method of production of vertical MOS transistor

Also Published As

Publication number Publication date
EP0583022B1 (de) 2003-01-08
EP0583022A3 (en) 1996-08-14
EP0583022A2 (de) 1994-02-16
DE69332619T2 (de) 2003-08-21
JP3413248B2 (ja) 2003-06-03
US5387528A (en) 1995-02-07
JPH06209013A (ja) 1994-07-26
GB9215653D0 (en) 1992-09-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee