DE69333173D1 - Verfahren zur Herstellung eines Substrates mit einer Halbleiterschicht auf einem Isolator - Google Patents

Verfahren zur Herstellung eines Substrates mit einer Halbleiterschicht auf einem Isolator

Info

Publication number
DE69333173D1
DE69333173D1 DE69333173T DE69333173T DE69333173D1 DE 69333173 D1 DE69333173 D1 DE 69333173D1 DE 69333173 T DE69333173 T DE 69333173T DE 69333173 T DE69333173 T DE 69333173T DE 69333173 D1 DE69333173 D1 DE 69333173D1
Authority
DE
Germany
Prior art keywords
insulator
producing
substrate
semiconductor layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69333173T
Other languages
English (en)
Other versions
DE69333173T2 (de
Inventor
Tetsuya Nakai
Yasuo Yamaguchi
Tadashi Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP04331426A external-priority patent/JP3091800B2/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69333173D1 publication Critical patent/DE69333173D1/de
Publication of DE69333173T2 publication Critical patent/DE69333173T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
DE69333173T 1992-02-18 1993-02-17 Verfahren zur Herstellung eines Substrates mit einer Halbleiterschicht auf einem Isolator Expired - Fee Related DE69333173T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP3060692 1992-02-18
JP3060692 1992-02-18
JP33142692 1992-12-11
JP04331426A JP3091800B2 (ja) 1992-02-18 1992-12-11 Ｓｏｉ基板の製造方法

Publications (2)

Publication Number Publication Date
DE69333173D1 true DE69333173D1 (de) 2003-10-09
DE69333173T2 DE69333173T2 (de) 2004-07-15

Family

ID=26368998

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69333173T Expired - Fee Related DE69333173T2 (de) 1992-02-18 1993-02-17 Verfahren zur Herstellung eines Substrates mit einer Halbleiterschicht auf einem Isolator

Country Status (3)

Country Link
US (2) US5441899A (de)
EP (1) EP0556795B1 (de)
DE (1) DE69333173T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3139904B2 (ja) * 1993-12-28 2001-03-05 新日本製鐵株式会社 半導体基板の製造方法および製造装置
US5468657A (en) * 1994-06-17 1995-11-21 Sharp Microelectronics Technology, Inc. Nitridation of SIMOX buried oxide
US5789284A (en) * 1994-09-29 1998-08-04 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating semiconductor thin film
USRE43450E1 (en) 1994-09-29 2012-06-05 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating semiconductor thin film
JP3204855B2 (ja) * 1994-09-30 2001-09-04 新日本製鐵株式会社 半導体基板の製造方法
US5589407A (en) * 1995-09-06 1996-12-31 Implanted Material Technology, Inc. Method of treating silicon to obtain thin, buried insulating layer
US5646053A (en) * 1995-12-20 1997-07-08 International Business Machines Corporation Method and structure for front-side gettering of silicon-on-insulator substrates
US6331457B1 (en) 1997-01-24 2001-12-18 Semiconductor Energy Laboratory., Ltd. Co. Method for manufacturing a semiconductor thin film
JPH09331049A (ja) * 1996-04-08 1997-12-22 Canon Inc 貼り合わせｓｏｉ基板の作製方法及びｓｏｉ基板
JP2856157B2 (ja) * 1996-07-16 1999-02-10 日本電気株式会社 半導体装置の製造方法
US5970350A (en) * 1996-12-05 1999-10-19 Advanced Micro Devices Semiconductor device having a thin gate oxide and method of manufacture thereof
JP3830623B2 (ja) 1997-07-14 2006-10-04 株式会社半導体エネルギー研究所 結晶性半導体膜の作製方法
JP3295346B2 (ja) 1997-07-14 2002-06-24 株式会社半導体エネルギー研究所 結晶性珪素膜の作製方法及びそれを用いた薄膜トランジスタ
US6133123A (en) 1997-08-21 2000-10-17 Micron Technology, Inc. Fabrication of semiconductor gettering structures by ion implantation
US5994759A (en) 1998-11-06 1999-11-30 National Semiconductor Corporation Semiconductor-on-insulator structure with reduced parasitic capacitance
US6753229B1 (en) 1998-12-04 2004-06-22 The Regents Of The University Of California Multiple-thickness gate oxide formed by oxygen implantation
US6248642B1 (en) 1999-06-24 2001-06-19 Ibis Technology Corporation SIMOX using controlled water vapor for oxygen implants
JP4437570B2 (ja) * 1999-07-12 2010-03-24 株式会社ルネサステクノロジ 半導体装置及び半導体装置の製造方法
US6593173B1 (en) 2000-11-28 2003-07-15 Ibis Technology Corporation Low defect density, thin-layer, SOI substrates
US20050118802A1 (en) * 2003-12-02 2005-06-02 Chang-Sheng Tsao Method for implementing poly pre-doping in deep sub-micron process
US7129138B1 (en) * 2005-04-14 2006-10-31 International Business Machines Corporation Methods of implementing and enhanced silicon-on-insulator (SOI) box structures
US7709313B2 (en) * 2005-07-19 2010-05-04 International Business Machines Corporation High performance capacitors in planar back gates CMOS
US9093538B2 (en) * 2011-04-08 2015-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
WO2012170027A1 (en) * 2011-06-09 2012-12-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for producing a field effect transistor with implantation through the spacers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE220812C (de) *
JPS57104239A (en) * 1980-12-22 1982-06-29 Nippon Telegr & Teleph Corp <Ntt> Forming method for insulating layer
JPS61144018A (ja) * 1984-12-18 1986-07-01 Fujitsu Ltd マスクレス・イオン注入法
FR2581795B1 (fr) * 1985-05-10 1988-06-17 Golanski Andrzej Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique
FR2591795B1 (fr) * 1985-12-16 1989-01-20 Europhane Procede de realisation de circuits magnetiques avec entrefer ajustable et circuits magnetiques ainsi obtenus
JPH0666385B2 (ja) * 1988-01-06 1994-08-24 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
US5441899A (en) 1995-08-15
DE69333173T2 (de) 2004-07-15
US5616507A (en) 1997-04-01
EP0556795A2 (de) 1993-08-25
EP0556795B1 (de) 2003-09-03
EP0556795A3 (en) 1996-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee