DE69407588T2 - Programmierbare digitale Verzögerungsschaltungseinheit - Google Patents

Programmierbare digitale Verzögerungsschaltungseinheit

Info

Publication number
DE69407588T2
DE69407588T2 DE69407588T DE69407588T DE69407588T2 DE 69407588 T2 DE69407588 T2 DE 69407588T2 DE 69407588 T DE69407588 T DE 69407588T DE 69407588 T DE69407588 T DE 69407588T DE 69407588 T2 DE69407588 T2 DE 69407588T2
Authority
DE
Germany
Prior art keywords
circuit unit
delay circuit
programmable digital
digital delay
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69407588T
Other languages
English (en)
Other versions
DE69407588D1 (de
Inventor
David Moloney
Paolo Gadducci
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Application granted granted Critical
Publication of DE69407588D1 publication Critical patent/DE69407588D1/de
Publication of DE69407588T2 publication Critical patent/DE69407588T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
DE69407588T 1994-09-21 1994-09-21 Programmierbare digitale Verzögerungsschaltungseinheit Expired - Fee Related DE69407588T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830445A EP0703663B1 (de) 1994-09-21 1994-09-21 Programmierbare digitale Verzögerungsschaltungseinheit

Publications (2)

Publication Number Publication Date
DE69407588D1 DE69407588D1 (de) 1998-02-05
DE69407588T2 true DE69407588T2 (de) 1998-07-09

Family

ID=8218528

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69407588T Expired - Fee Related DE69407588T2 (de) 1994-09-21 1994-09-21 Programmierbare digitale Verzögerungsschaltungseinheit

Country Status (3)

Country Link
US (1) US5670904A (de)
EP (1) EP0703663B1 (de)
DE (1) DE69407588T2 (de)

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US5731726A (en) * 1995-05-25 1998-03-24 Hughes Electronics Controllable precision on-chip delay element
US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
DE19845115C2 (de) * 1998-09-30 2000-08-31 Siemens Ag Integrierte Schaltung mit einer einstellbaren Verzögerungseinheit
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6380785B2 (en) * 1999-02-01 2002-04-30 Agilent Technologies, Inc. Method and apparatus for eliminating shoot-through events during master-slave flip-flop scan operations
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6629250B2 (en) 1999-04-23 2003-09-30 Cray Inc. Adjustable data delay using programmable clock shift
US6557066B1 (en) 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
US6294937B1 (en) 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
US6169438B1 (en) * 1999-09-20 2001-01-02 Oak Technology, Inc. Circuit and method for selectively delaying electrical signals
US6285229B1 (en) * 1999-12-23 2001-09-04 International Business Machines Corp. Digital delay line with low insertion delay
US6892315B1 (en) * 2000-05-24 2005-05-10 Cypress Semiconductor Corp. Adjustable microcontroller wake-up scheme that calibrates a programmable delay value based on a measured delay
US6907539B1 (en) * 2000-06-13 2005-06-14 Cypress Semiconductor Corp. Configurage data setup/hold timing circuit with user programmable delay
DE10035424A1 (de) * 2000-07-20 2002-01-31 Infineon Technologies Ag Zwischenspeichereinrichtung
US7805628B2 (en) * 2001-04-02 2010-09-28 Credence Systems Corporation High resolution clock signal generator
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US20030048122A1 (en) * 2001-09-10 2003-03-13 Tauseef Kazi Universal programmable delay cell
US6710637B1 (en) * 2002-04-29 2004-03-23 National Semiconductor Corporation Non-overlap clock circuit
JP4288066B2 (ja) 2002-12-27 2009-07-01 エヌエックスピー ビー ヴィ 回路装置
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US6876717B1 (en) * 2004-08-19 2005-04-05 Intel Corporation Multi-stage programmable Johnson counter
JP4019079B2 (ja) * 2004-12-28 2007-12-05 エルピーダメモリ株式会社 遅延回路及び半導体装置
US7355435B2 (en) * 2005-02-10 2008-04-08 International Business Machines Corporation On-chip detection of power supply vulnerabilities
US20060176096A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation Power supply insensitive delay element
US7279949B2 (en) * 2005-02-11 2007-10-09 International Business Machines Corporation Programmable delay element
TWI358694B (en) * 2006-09-12 2012-02-21 Himax Semiconductor Inc Operating frequency generating method and circuit
US8023612B2 (en) * 2008-09-25 2011-09-20 Cisco Technology, Inc. Shift register with dynamic entry point particularly useful for aligning skewed data
US8004329B1 (en) * 2010-03-19 2011-08-23 National Semiconductor Corporation Hardware performance monitor (HPM) with variable resolution for adaptive voltage scaling (AVS) systems
US8572426B2 (en) 2010-05-27 2013-10-29 National Semiconductor Corporation Hardware performance monitor (HPM) with extended resolution for adaptive voltage scaling (AVS) systems
GB201015729D0 (en) 2010-09-20 2010-10-27 Novelda As Pulse generator
GB201015730D0 (en) 2010-09-20 2010-10-27 Novelda As Continuous time cross-correlator
US8693616B1 (en) * 2012-03-27 2014-04-08 Altera Corporation IC and a method for flexible integer and fractional divisions
US9118310B1 (en) * 2014-09-10 2015-08-25 Xilinx, Inc. Programmable delay circuit block
US11468958B1 (en) * 2021-06-11 2022-10-11 Winbond Electronics Corp. Shift register circuit and a method for controlling a shift register circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4820944A (en) * 1983-08-01 1989-04-11 Schlumberger Systems & Services, Inc. Method and apparatus for dynamically controlling the timing of signals in automatic test systems
JP2539600B2 (ja) * 1985-07-10 1996-10-02 株式会社アドバンテスト タイミング発生装置
JP2582250B2 (ja) * 1986-10-03 1997-02-19 日本電信電話株式会社 タイミング信号遅延回路装置
US4894626A (en) * 1988-09-30 1990-01-16 Advanced Micro Devices, Inc. Variable length shift register
US5258660A (en) * 1990-01-16 1993-11-02 Cray Research, Inc. Skew-compensated clock distribution system
JPH03268563A (ja) * 1990-03-16 1991-11-29 Mita Ind Co Ltd レーザビーム制御装置
DE4110340C2 (de) * 1990-04-16 1993-11-25 Tektronix Inc Aktive ansteuerbare digitale Verzögerungsschaltung
US5204559A (en) * 1991-01-23 1993-04-20 Vitesse Semiconductor Corporation Method and apparatus for controlling clock skew
US5389843A (en) * 1992-08-28 1995-02-14 Tektronix, Inc. Simplified structure for programmable delays
US5459422A (en) * 1993-06-02 1995-10-17 Advanced Micro Devices, Inc. Edge selective delay circuit

Also Published As

Publication number Publication date
EP0703663A1 (de) 1996-03-27
DE69407588D1 (de) 1998-02-05
US5670904A (en) 1997-09-23
EP0703663B1 (de) 1997-12-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee