DE69408749T2 - Verfahren und Vorrichtung zur digitalen Zeitverzögerung - Google Patents

Verfahren und Vorrichtung zur digitalen Zeitverzögerung

Info

Publication number
DE69408749T2
DE69408749T2 DE69408749T DE69408749T DE69408749T2 DE 69408749 T2 DE69408749 T2 DE 69408749T2 DE 69408749 T DE69408749 T DE 69408749T DE 69408749 T DE69408749 T DE 69408749T DE 69408749 T2 DE69408749 T2 DE 69408749T2
Authority
DE
Germany
Prior art keywords
time delay
digital time
digital
delay
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69408749T
Other languages
English (en)
Other versions
DE69408749D1 (de
Inventor
Bin Guo
Jim Kubinec
Eugen Gershon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69408749D1 publication Critical patent/DE69408749D1/de
Publication of DE69408749T2 publication Critical patent/DE69408749T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0058—Detection of the synchronisation error by features other than the received signal transition detection of error based on equalizer tap values
DE69408749T 1993-08-11 1994-07-07 Verfahren und Vorrichtung zur digitalen Zeitverzögerung Expired - Fee Related DE69408749T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/105,079 US5457719A (en) 1993-08-11 1993-08-11 All digital on-the-fly time delay calibrator

Publications (2)

Publication Number Publication Date
DE69408749D1 DE69408749D1 (de) 1998-04-09
DE69408749T2 true DE69408749T2 (de) 1998-09-17

Family

ID=22303935

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69408749T Expired - Fee Related DE69408749T2 (de) 1993-08-11 1994-07-07 Verfahren und Vorrichtung zur digitalen Zeitverzögerung

Country Status (6)

Country Link
US (1) US5457719A (de)
EP (1) EP0639004B1 (de)
JP (1) JPH07154245A (de)
KR (1) KR950007336A (de)
DE (1) DE69408749T2 (de)
TW (1) TW230856B (de)

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US5774403A (en) * 1997-06-12 1998-06-30 Hewlett-Packard PVT self aligning internal delay line and method of operation
US5903521A (en) * 1997-07-11 1999-05-11 Advanced Micro Devices, Inc. Floating point timer
US6122278A (en) * 1997-08-07 2000-09-19 Advanced Micro Devices, Inc. Circuit and method for protocol header decoding and packet routing
US5943206A (en) * 1997-08-19 1999-08-24 Advanced Micro Devices, Inc. Chip temperature protection using delay lines
US5890100A (en) * 1997-08-19 1999-03-30 Advanced Micro Devices, Inc. Chip temperature monitor using delay lines
FR2768575B1 (fr) * 1997-09-12 2004-04-09 Sgs Thomson Microelectronics Procede de mesure de delai temporel et circuit mettant en oeuvre le procede
US6192069B1 (en) 1997-11-03 2001-02-20 Advanced Micro Devices, Inc. Circuit and methodology for transferring signals between semiconductor devices
US6084933A (en) * 1997-11-17 2000-07-04 Advanced Micro Devices, Inc. Chip operating conditions compensated clock generation
US5852616A (en) * 1997-11-17 1998-12-22 Advanced Micro Devices, Inc. On-chip operating condition recorder
US6031473A (en) * 1997-11-17 2000-02-29 Advanced Micro Devices, Inc. Digital communications using serialized delay line
US5942937A (en) * 1997-11-19 1999-08-24 Advanced Micro Devices, Inc. Signal detection circuit using a plurality of delay stages with edge detection logic
US6163759A (en) * 1997-11-21 2000-12-19 Advantest Corporation Method for calibrating variable delay circuit and a variable delay circuit using the same
US6064232A (en) * 1997-12-18 2000-05-16 Advanced Micro Devices, Inc. Self-clocked logic circuit and methodology
US6160856A (en) * 1997-12-18 2000-12-12 Advanced Micro Devices, Inc. System for providing amplitude and phase modulation of line signals using delay lines
US6218880B1 (en) 1997-12-18 2001-04-17 Legerity Analog delay line implemented with a digital delay line technique
US6091348A (en) * 1997-12-18 2000-07-18 Advanced Micro Devices, Inc. Circuit and method for on-the-fly bit detection and substitution
US6178208B1 (en) 1997-12-18 2001-01-23 Legerity System for recovery of digital data from amplitude and phase modulated line signals using delay lines
US5900834A (en) * 1997-12-18 1999-05-04 Advanced Micro Devices, Inc. Doppler shift detector
US6078627A (en) * 1997-12-18 2000-06-20 Advanced Micro Devices, Inc. Circuit and method for multilevel signal decoding, descrambling, and error detection
US6046620A (en) * 1997-12-18 2000-04-04 Advanced Micro Devices, Inc. Programmable delay line
US6255969B1 (en) * 1997-12-18 2001-07-03 Advanced Micro Devices, Inc. Circuit and method for high speed bit stream capture using a digital delay line
US6222392B1 (en) 1998-04-17 2001-04-24 Advanced Micro Devices, Inc. Signal monitoring circuit for detecting asynchronous clock loss
US6339833B1 (en) 1998-04-17 2002-01-15 Advanced Micro Devices, Inc. Automatic recovery from clock signal loss
DE19830570A1 (de) 1998-07-08 2000-01-20 Siemens Ag Schaltung zur Ermittlung der Zeitdifferenz zwischen Flanken eines ersten und eines zweiten digitalen Signals
EP0987853A1 (de) * 1998-09-17 2000-03-22 STMicroelectronics S.r.l. Vollständig digitaler Phasenausrichter
US7010370B1 (en) * 1999-08-30 2006-03-07 Creative Technology, Ltd. System and method for adjusting delay of an audio signal
US6693436B1 (en) * 1999-12-23 2004-02-17 Intel Corporation Method and apparatus for testing an integrated circuit having an output-to-output relative signal
US6654900B1 (en) * 2000-04-19 2003-11-25 Sigmatel, Inc. Method and apparatus for producing multiple clock signals having controlled duty cycles by controlling clock multiplier delay elements
US6348828B1 (en) 2000-09-29 2002-02-19 Agilent Technologies, Inc. Clock enable circuit for use in a high speed reprogrammable delay line incorporating glitchless enable/disable functionality
US6373312B1 (en) 2000-09-29 2002-04-16 Agilent Technologies, Inc. Precision, high speed delay system for providing delayed clock edges with new delay values every clock period
US6535735B2 (en) * 2001-03-22 2003-03-18 Skyworks Solutions, Inc. Critical path adaptive power control
US6931075B2 (en) * 2001-04-05 2005-08-16 Microchip Technology Incorporated Event detection with a digital processor
DE10128757B4 (de) * 2001-06-13 2005-03-03 Infineon Technologies Ag Verfahren und Schaltungsanordnung zum Regeln der Betriebsspannung einer Digitalschaltung
JP2003050738A (ja) * 2001-08-03 2003-02-21 Elpida Memory Inc キャリブレーション方法及びメモリシステム
US7120215B2 (en) * 2001-12-12 2006-10-10 Via Technologies, Inc. Apparatus and method for on-chip jitter measurement
KR100543925B1 (ko) * 2003-06-27 2006-01-23 주식회사 하이닉스반도체 지연 고정 루프 및 지연 고정 루프에서의 클럭 지연 고정방법
US7275011B2 (en) * 2005-06-30 2007-09-25 International Business Machines Corporation Method and apparatus for monitoring integrated circuit temperature through deterministic path delays
US7446612B2 (en) * 2006-09-08 2008-11-04 Skyworks Solutions, Inc. Amplifier feedback and bias configuration
US7696826B2 (en) * 2006-12-04 2010-04-13 Skyworks Solutions, Inc. Temperature compensation of collector-voltage control RF amplifiers
US8615767B2 (en) 2007-02-06 2013-12-24 International Business Machines Corporation Using IR drop data for instruction thread direction
US7714635B2 (en) * 2007-02-06 2010-05-11 International Business Machines Corporation Digital adaptive voltage supply
US7971035B2 (en) 2007-02-06 2011-06-28 International Business Machines Corporation Using temperature data for instruction thread direction
US7936153B2 (en) 2007-02-06 2011-05-03 International Business Machines Corporation On-chip adaptive voltage compensation
US7779235B2 (en) 2007-02-06 2010-08-17 International Business Machines Corporation Using performance data for instruction thread direction
US8022685B2 (en) 2007-02-06 2011-09-20 International Business Machines Corporation Temperature dependent voltage source compensation
US7895454B2 (en) 2007-02-06 2011-02-22 International Business Machines Corporation Instruction dependent dynamic voltage compensation
US7865750B2 (en) * 2007-02-06 2011-01-04 International Business Machines Corporation Fan speed control from adaptive voltage supply
EP2115384B1 (de) * 2007-02-16 2015-03-25 Orica Explosives Technology Pty Ltd Sprengzünder, sprengvorrichtung und entsprechendes verfahren
US8005880B2 (en) * 2007-08-24 2011-08-23 International Business Machines Corporation Half width counting leading zero circuit
US7797131B2 (en) * 2007-08-24 2010-09-14 International Business Machines Corporation On-chip frequency response measurement
US8185572B2 (en) * 2007-08-24 2012-05-22 International Business Machines Corporation Data correction circuit
EP2704339B1 (de) * 2012-09-04 2017-11-22 OCT Circuit Technologies International Limited Integriertes Selbsttestverfahren zur Erkennung von unvollkommen angeschlossenen Antennen in OFDM-Transceivern
KR102512819B1 (ko) * 2016-04-19 2023-03-23 삼성전자주식회사 딜레이 코드를 발생하는 전압 모니터

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US5036528A (en) * 1990-01-29 1991-07-30 Tandem Computers Incorporated Self-calibrating clock synchronization system
GB2241620B (en) * 1990-02-13 1994-11-30 Matsushita Electric Ind Co Ltd A pulse signal delay device
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US5245637A (en) * 1991-12-30 1993-09-14 International Business Machines Corporation Phase and frequency adjustable digital phase lock logic system
US5534808A (en) * 1992-01-31 1996-07-09 Konica Corporation Signal delay method, signal delay device and circuit for use in the apparatus
US5281874A (en) * 1992-02-14 1994-01-25 Vlsi Technology, Inc. Compensated digital delay semiconductor device with selectable output taps and method therefor
US5313503A (en) * 1992-06-25 1994-05-17 International Business Machines Corporation Programmable high speed digital phase locked loop

Also Published As

Publication number Publication date
US5457719A (en) 1995-10-10
KR950007336A (ko) 1995-03-21
EP0639004A1 (de) 1995-02-15
DE69408749D1 (de) 1998-04-09
TW230856B (en) 1994-09-21
EP0639004B1 (de) 1998-03-04
JPH07154245A (ja) 1995-06-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee