DE69412652D1 - Übermittlung von logischen Signalen sehr niedriger Spannung zwischen CMOS-Chips für eine grosse Anzahl Hochgeschwindigkeitsausgangsleitungen mit jeweils grosser kapazitiver Last - Google Patents

Übermittlung von logischen Signalen sehr niedriger Spannung zwischen CMOS-Chips für eine grosse Anzahl Hochgeschwindigkeitsausgangsleitungen mit jeweils grosser kapazitiver Last

Info

Publication number
DE69412652D1
DE69412652D1 DE69412652T DE69412652T DE69412652D1 DE 69412652 D1 DE69412652 D1 DE 69412652D1 DE 69412652 T DE69412652 T DE 69412652T DE 69412652 T DE69412652 T DE 69412652T DE 69412652 D1 DE69412652 D1 DE 69412652D1
Authority
DE
Germany
Prior art keywords
transmission
low voltage
output lines
capacitive load
speed output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69412652T
Other languages
English (en)
Other versions
DE69412652T2 (de
Inventor
Frank M Wanlass
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Standard Microsystems LLC
Original Assignee
Standard Microsystems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Microsystems LLC filed Critical Standard Microsystems LLC
Application granted granted Critical
Publication of DE69412652D1 publication Critical patent/DE69412652D1/de
Publication of DE69412652T2 publication Critical patent/DE69412652T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018592—Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation
DE69412652T 1993-01-25 1994-01-22 Übermittlung von logischen Signalen sehr niedriger Spannung zwischen CMOS-Chips für eine grosse Anzahl Hochgeschwindigkeitsausgangsleitungen mit jeweils grosser kapazitiver Last Expired - Fee Related DE69412652T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/008,669 US5311083A (en) 1993-01-25 1993-01-25 Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads

Publications (2)

Publication Number Publication Date
DE69412652D1 true DE69412652D1 (de) 1998-10-01
DE69412652T2 DE69412652T2 (de) 1999-04-15

Family

ID=21732982

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69412652T Expired - Fee Related DE69412652T2 (de) 1993-01-25 1994-01-22 Übermittlung von logischen Signalen sehr niedriger Spannung zwischen CMOS-Chips für eine grosse Anzahl Hochgeschwindigkeitsausgangsleitungen mit jeweils grosser kapazitiver Last

Country Status (5)

Country Link
US (1) US5311083A (de)
EP (1) EP0608786B1 (de)
JP (1) JP3512223B2 (de)
CA (1) CA2113987A1 (de)
DE (1) DE69412652T2 (de)

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US5406143A (en) * 1993-12-21 1995-04-11 Vertex Semiconductor Corporation GTL to CMOS level signal converter, method and apparatus
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US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
FR2725085B1 (fr) * 1994-09-26 1997-01-17 Matra Mhs Dispositif d'interfacage de signaux logiques du niveau btl au niveau ttl et cmos
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US5604450A (en) * 1995-07-27 1997-02-18 Intel Corporation High speed bidirectional signaling scheme
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US5585744A (en) * 1995-10-13 1996-12-17 Cirrus Logic, Inc. Circuits systems and methods for reducing power loss during transfer of data across a conductive line
KR0166509B1 (ko) * 1995-12-29 1999-01-15 김주용 정전기 보호 회로
CN1183587C (zh) 1996-04-08 2005-01-05 德克萨斯仪器股份有限公司 用于把两个集成电路直流上相互隔离的方法和设备
JP3195913B2 (ja) * 1996-04-30 2001-08-06 株式会社東芝 半導体集積回路装置
US6118302A (en) 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
US6175952B1 (en) * 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US8604828B1 (en) * 1996-05-31 2013-12-10 International Business Machines Corporation Variable voltage CMOS off-chip driver and receiver circuits
US5723987A (en) * 1996-06-06 1998-03-03 Intel Corporation Level shifting output buffer with p channel pulldown transistors which are bypassed
US5952847A (en) * 1996-06-25 1999-09-14 Actel Corporation Multiple logic family compatible output driver
US5818261A (en) * 1996-08-08 1998-10-06 Hewlett Packard Company Pseudo differential bus driver/receiver for field programmable devices
US6552594B2 (en) * 1997-03-27 2003-04-22 Winbond Electronics, Corp. Output buffer with improved ESD protection
JPH1155107A (ja) * 1997-08-04 1999-02-26 Hitachi Ltd 半導体集積回路装置
US6078192A (en) * 1997-09-18 2000-06-20 Ericsson, Inc. Circuit and method for using the I2 C serial protocol with multiple voltages
JPH11102305A (ja) * 1997-09-29 1999-04-13 Oki Electric Ind Co Ltd インサーキットエミュレータ
US6107856A (en) * 1997-12-30 2000-08-22 Lsi Logic Corporation Dual output comparator for operating over a wide common mode range
US6181165B1 (en) * 1998-03-09 2001-01-30 Siemens Aktiengesellschaft Reduced voltage input/reduced voltage output tri-state buffers
US6064226A (en) * 1998-03-17 2000-05-16 Vanguard International Semiconductor Corporation Multiple input/output level interface input receiver
US5991135A (en) * 1998-05-11 1999-11-23 Vlsi Technology, Inc. System including ESD protection
US6507471B2 (en) 2000-12-07 2003-01-14 Koninklijke Philips Electronics N.V. ESD protection devices
JP3916986B2 (ja) * 2001-05-18 2007-05-23 シャープ株式会社 信号処理回路、低電圧信号発生器およびそれを備えた画像表示装置
US6693780B2 (en) 2001-08-02 2004-02-17 Koninklijke Philips Electronics N.V. ESD protection devices for a differential pair of transistors
JP3786608B2 (ja) * 2002-01-28 2006-06-14 株式会社ルネサステクノロジ 半導体集積回路装置
US7098693B2 (en) * 2004-08-31 2006-08-29 International Business Machines Corporation Bi-directional voltage translator
US7560798B2 (en) * 2006-02-27 2009-07-14 International Business Machines Corporation High performance tapered varactor
JP5040587B2 (ja) * 2007-10-25 2012-10-03 ソニー株式会社 高周波回路装置
JP4602443B2 (ja) * 2008-08-18 2010-12-22 ルネサスエレクトロニクス株式会社 半導体集積回路
US8159270B2 (en) * 2008-10-28 2012-04-17 Micron Technology, Inc. Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled by a third power supply
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US5023487A (en) * 1989-09-29 1991-06-11 Texas Instruments Incorporated ECL/TTL-CMOS translator bus interface architecture
US5023488A (en) * 1990-03-30 1991-06-11 Xerox Corporation Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines
JPH04155693A (ja) * 1990-10-18 1992-05-28 Nec Ic Microcomput Syst Ltd 半導体記憶装置のデータ出力回路

Also Published As

Publication number Publication date
DE69412652T2 (de) 1999-04-15
JPH077409A (ja) 1995-01-10
EP0608786A1 (de) 1994-08-03
US5311083A (en) 1994-05-10
EP0608786B1 (de) 1998-08-26
JP3512223B2 (ja) 2004-03-29
CA2113987A1 (en) 1994-07-26

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee