DE69421233D1 - Integrierte Halbleiterschaltungsanordnung mit Eingangsignalschaltung von niedriger Leistung, reagierend auf ein sehr schnelles Eingangsignal von niedriger Intensität - Google Patents

Integrierte Halbleiterschaltungsanordnung mit Eingangsignalschaltung von niedriger Leistung, reagierend auf ein sehr schnelles Eingangsignal von niedriger Intensität

Info

Publication number
DE69421233D1
DE69421233D1 DE69421233T DE69421233T DE69421233D1 DE 69421233 D1 DE69421233 D1 DE 69421233D1 DE 69421233 T DE69421233 T DE 69421233T DE 69421233 T DE69421233 T DE 69421233T DE 69421233 D1 DE69421233 D1 DE 69421233D1
Authority
DE
Germany
Prior art keywords
input signal
fast
integrated semiconductor
low power
power input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69421233T
Other languages
English (en)
Other versions
DE69421233T2 (de
Inventor
Takashi Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69421233D1 publication Critical patent/DE69421233D1/de
Application granted granted Critical
Publication of DE69421233T2 publication Critical patent/DE69421233T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
DE69421233T 1993-08-26 1994-08-23 Integrierte Halbleiterschaltungsanordnung mit Eingangsignalschaltung von niedriger Leistung, reagierend auf ein sehr schnelles Eingangsignal von niedriger Intensität Expired - Lifetime DE69421233T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5211323A JP2836453B2 (ja) 1993-08-26 1993-08-26 半導体メモリの初段回路方式

Publications (2)

Publication Number Publication Date
DE69421233D1 true DE69421233D1 (de) 1999-11-25
DE69421233T2 DE69421233T2 (de) 2000-05-31

Family

ID=16604056

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69421233T Expired - Lifetime DE69421233T2 (de) 1993-08-26 1994-08-23 Integrierte Halbleiterschaltungsanordnung mit Eingangsignalschaltung von niedriger Leistung, reagierend auf ein sehr schnelles Eingangsignal von niedriger Intensität

Country Status (5)

Country Link
US (1) US5469386A (de)
EP (1) EP0640981B1 (de)
JP (1) JP2836453B2 (de)
KR (1) KR0132633B1 (de)
DE (1) DE69421233T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3540844B2 (ja) * 1994-11-02 2004-07-07 日本テキサス・インスツルメンツ株式会社 半導体集積回路
JP3592386B2 (ja) * 1994-11-22 2004-11-24 株式会社ルネサステクノロジ 同期型半導体記憶装置
EP0732699B1 (de) * 1995-03-14 2001-09-05 Nec Corporation Interner Taktgenerator für einen synchronen dynamischen RAM Speicher
US5710933A (en) * 1995-03-31 1998-01-20 International Business Machines Corporation System resource enable apparatus
JP3986578B2 (ja) * 1996-01-17 2007-10-03 三菱電機株式会社 同期型半導体記憶装置
US5749086A (en) * 1996-02-29 1998-05-05 Micron Technology, Inc. Simplified clocked DRAM with a fast command input
JP4000206B2 (ja) * 1996-08-29 2007-10-31 富士通株式会社 半導体記憶装置
US5870049A (en) * 1997-04-16 1999-02-09 Mosaid Technologies Incorporated Current mode digital to analog converter
US6801069B1 (en) * 1998-05-04 2004-10-05 International Business Machines Corporation Receiving latch with hysteresis
JP3125749B2 (ja) * 1998-06-11 2001-01-22 日本電気株式会社 同期型半導体メモリ
DE19829288C2 (de) 1998-06-30 2001-03-01 Siemens Ag Dynamische Halbleiter-Speichervorrichtung und Verfahren zur Initialisierung einer dynamischen Halbleiter-Speichervorrichtung
US6334167B1 (en) 1998-08-31 2001-12-25 International Business Machines Corporation System and method for memory self-timed refresh for reduced power consumption
KR100317319B1 (ko) * 1999-05-19 2001-12-22 김영환 메모리 소자의 저전력 구동 회로
JP2002216472A (ja) 2001-01-22 2002-08-02 Nec Corp 半導体記憶装置
JP4317353B2 (ja) * 2001-10-19 2009-08-19 三星電子株式会社 メモリシステムの能動終端抵抗の制御装置及び方法
JP6409590B2 (ja) * 2015-01-22 2018-10-24 富士ゼロックス株式会社 情報処理装置及びプログラム
US10607681B2 (en) * 2018-06-28 2020-03-31 Micron Technology, Inc. Apparatuses and methods for switching refresh state in a memory circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873096A (ja) * 1981-10-27 1983-05-02 Nec Corp 半導体メモリ
JPH0632220B2 (ja) * 1984-10-16 1994-04-27 三菱電機株式会社 半導体記憶装置のセンスアンプ
JP2621140B2 (ja) * 1986-06-20 1997-06-18 三菱電機株式会社 センスアンプ回路
JP2617779B2 (ja) * 1988-08-31 1997-06-04 三菱電機株式会社 半導体メモリ装置
US5335201A (en) * 1991-04-15 1994-08-02 Micron Technology, Inc. Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs
KR920022293A (ko) * 1991-05-16 1992-12-19 김광호 비정기적인 리프레쉬 동작을 실행하는 반도체 메모리 장치
JPH05266657A (ja) * 1992-03-23 1993-10-15 Nec Corp ダイナミック型半導体メモリ

Also Published As

Publication number Publication date
EP0640981A2 (de) 1995-03-01
JPH0765574A (ja) 1995-03-10
JP2836453B2 (ja) 1998-12-14
KR950007089A (ko) 1995-03-21
KR0132633B1 (ko) 1998-04-16
EP0640981A3 (de) 1995-06-28
DE69421233T2 (de) 2000-05-31
EP0640981B1 (de) 1999-10-20
US5469386A (en) 1995-11-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP