DE69421925T2 - Speichergerät mit Fehlerdetektion und -korrektur und Verfahren zum Schreiben und Löschen des Speichergeräts - Google Patents

Speichergerät mit Fehlerdetektion und -korrektur und Verfahren zum Schreiben und Löschen des Speichergeräts

Info

Publication number
DE69421925T2
DE69421925T2 DE69421925T DE69421925T DE69421925T2 DE 69421925 T2 DE69421925 T2 DE 69421925T2 DE 69421925 T DE69421925 T DE 69421925T DE 69421925 T DE69421925 T DE 69421925T DE 69421925 T2 DE69421925 T2 DE 69421925T2
Authority
DE
Germany
Prior art keywords
data
address
storage device
designed
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69421925T
Other languages
English (en)
Other versions
DE69421925D1 (de
Inventor
Livio Baldi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69421925D1 publication Critical patent/DE69421925D1/de
Application granted granted Critical
Publication of DE69421925T2 publication Critical patent/DE69421925T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
DE69421925T 1994-09-30 1994-09-30 Speichergerät mit Fehlerdetektion und -korrektur und Verfahren zum Schreiben und Löschen des Speichergeräts Expired - Fee Related DE69421925T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830471A EP0704854B1 (de) 1994-09-30 1994-09-30 Speichergerät mit Fehlerdetektion und -korrektur und Verfahren zum Schreiben und Löschen des Speichergeräts

Publications (2)

Publication Number Publication Date
DE69421925D1 DE69421925D1 (de) 2000-01-05
DE69421925T2 true DE69421925T2 (de) 2000-03-16

Family

ID=8218548

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69421925T Expired - Fee Related DE69421925T2 (de) 1994-09-30 1994-09-30 Speichergerät mit Fehlerdetektion und -korrektur und Verfahren zum Schreiben und Löschen des Speichergeräts

Country Status (4)

Country Link
US (1) US5761222A (de)
EP (1) EP0704854B1 (de)
JP (1) JP3704184B2 (de)
DE (1) DE69421925T2 (de)

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US5859858A (en) * 1996-10-25 1999-01-12 Intel Corporation Method and apparatus for correcting a multilevel cell memory by using error locating codes
US6212654B1 (en) 1997-07-22 2001-04-03 Lucent Technologies Inc. Coded modulation for digital storage in analog memory devices
KR100333720B1 (ko) * 1998-06-30 2002-06-20 박종섭 강유전체메모리소자의리던던시회로
WO2000041182A1 (en) * 1998-12-30 2000-07-13 Intel Corporation Memory array organization
US6647151B1 (en) * 1999-08-18 2003-11-11 Hewlett-Packard Development Company, L.P. Coalescence of device independent bitmaps for artifact avoidance
US6532556B1 (en) 2000-01-27 2003-03-11 Multi Level Memory Technology Data management for multi-bit-per-cell memories
US6466476B1 (en) 2001-01-18 2002-10-15 Multi Level Memory Technology Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell
US6700827B2 (en) 2001-02-08 2004-03-02 Integrated Device Technology, Inc. Cam circuit with error correction
US7630237B2 (en) 2003-02-06 2009-12-08 Sandisk Corporation System and method for programming cells in non-volatile integrated memory devices
US6870749B1 (en) 2003-07-15 2005-03-22 Integrated Device Technology, Inc. Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors
US6987684B1 (en) 2003-07-15 2006-01-17 Integrated Device Technology, Inc. Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein
US7193876B1 (en) 2003-07-15 2007-03-20 Kee Park Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors
US7304875B1 (en) 2003-12-17 2007-12-04 Integrated Device Technology. Inc. Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same
US6888758B1 (en) * 2004-01-21 2005-05-03 Sandisk Corporation Programming non-volatile memory
US7372730B2 (en) * 2004-01-26 2008-05-13 Sandisk Corporation Method of reading NAND memory to compensate for coupling between storage elements
US7002843B2 (en) * 2004-01-27 2006-02-21 Sandisk Corporation Variable current sinking for coarse/fine programming of non-volatile memory
US7068539B2 (en) * 2004-01-27 2006-06-27 Sandisk Corporation Charge packet metering for coarse/fine programming of non-volatile memory
US7139198B2 (en) * 2004-01-27 2006-11-21 Sandisk Corporation Efficient verification for coarse/fine programming of non-volatile memory
US7020026B2 (en) * 2004-05-05 2006-03-28 Sandisk Corporation Bitline governed approach for program control of non-volatile memory
US7023733B2 (en) * 2004-05-05 2006-04-04 Sandisk Corporation Boosting to control programming of non-volatile memory
US7099221B2 (en) * 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) * 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US7116602B2 (en) 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US6965537B1 (en) * 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
US7092290B2 (en) * 2004-11-16 2006-08-15 Sandisk Corporation High speed programming system with reduced over programming
US7173859B2 (en) * 2004-11-16 2007-02-06 Sandisk Corporation Faster programming of higher level states in multi-level cell flash memory
US7339834B2 (en) * 2005-06-03 2008-03-04 Sandisk Corporation Starting program voltage shift with cycling of non-volatile memory
US7206235B1 (en) 2005-10-14 2007-04-17 Sandisk Corporation Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling
US7286406B2 (en) * 2005-10-14 2007-10-23 Sandisk Corporation Method for controlled programming of non-volatile memory exhibiting bit line coupling
WO2007126665A1 (en) 2006-04-12 2007-11-08 Sandisk Corporation Reducing the impact of program disturb during read
US7486561B2 (en) * 2006-06-22 2009-02-03 Sandisk Corporation Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages
US7489549B2 (en) * 2006-06-22 2009-02-10 Sandisk Corporation System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages
US7450426B2 (en) * 2006-10-10 2008-11-11 Sandisk Corporation Systems utilizing variable program voltage increment values in non-volatile memory program operations
US7474561B2 (en) * 2006-10-10 2009-01-06 Sandisk Corporation Variable program voltage increment values in non-volatile memory program operations
US7894289B2 (en) 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
US7570520B2 (en) * 2006-12-27 2009-08-04 Sandisk Corporation Non-volatile storage system with initial programming voltage based on trial
US7551482B2 (en) * 2006-12-27 2009-06-23 Sandisk Corporation Method for programming with initial programming voltage based on trial
US8365044B2 (en) * 2007-04-23 2013-01-29 Agere Systems Inc. Memory device with error correction based on automatic logic inversion
US7599224B2 (en) * 2007-07-03 2009-10-06 Sandisk Corporation Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7508715B2 (en) * 2007-07-03 2009-03-24 Sandisk Corporation Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7949913B2 (en) 2007-08-14 2011-05-24 Dell Products L.P. Method for creating a memory defect map and optimizing performance using the memory defect map
US7945815B2 (en) 2007-08-14 2011-05-17 Dell Products L.P. System and method for managing memory errors in an information handling system
US7694195B2 (en) 2007-08-14 2010-04-06 Dell Products L.P. System and method for using a memory mapping function to map memory defects
US9373362B2 (en) 2007-08-14 2016-06-21 Dell Products L.P. System and method for implementing a memory defect map
US8625320B1 (en) 2010-08-31 2014-01-07 Netlogic Microsystems, Inc. Quaternary content addressable memory cell having one transistor pull-down stack
US8462532B1 (en) 2010-08-31 2013-06-11 Netlogic Microsystems, Inc. Fast quaternary content addressable memory cell
US8582338B1 (en) 2010-08-31 2013-11-12 Netlogic Microsystems, Inc. Ternary content addressable memory cell having single transistor pull-down stack
US8553441B1 (en) 2010-08-31 2013-10-08 Netlogic Microsystems, Inc. Ternary content addressable memory cell having two transistor pull-down stack
US8773880B2 (en) 2011-06-23 2014-07-08 Netlogic Microsystems, Inc. Content addressable memory array having virtual ground nodes
US8837188B1 (en) 2011-06-23 2014-09-16 Netlogic Microsystems, Inc. Content addressable memory row having virtual ground and charge sharing
US8724408B2 (en) 2011-11-29 2014-05-13 Kingtiger Technology (Canada) Inc. Systems and methods for testing and assembling memory modules
US9117552B2 (en) 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory
US10387251B2 (en) * 2017-07-17 2019-08-20 Cisco Technology, Inc. Error detection and correction in a content-addressable memory using single-bit position lookup operations

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US4654847A (en) * 1984-12-28 1987-03-31 International Business Machines Apparatus for automatically correcting erroneous data and for storing the corrected data in a common pool alternate memory array
JPH04177700A (ja) * 1990-11-13 1992-06-24 Toshiba Corp メモリ不良解析装置

Also Published As

Publication number Publication date
DE69421925D1 (de) 2000-01-05
EP0704854B1 (de) 1999-12-01
EP0704854A1 (de) 1996-04-03
JPH08123737A (ja) 1996-05-17
JP3704184B2 (ja) 2005-10-05
US5761222A (en) 1998-06-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee