DE69427959D1 - Integrierte Schaltung mit verbesserter Kontaktbarriere - Google Patents

Integrierte Schaltung mit verbesserter Kontaktbarriere

Info

Publication number
DE69427959D1
DE69427959D1 DE69427959T DE69427959T DE69427959D1 DE 69427959 D1 DE69427959 D1 DE 69427959D1 DE 69427959 T DE69427959 T DE 69427959T DE 69427959 T DE69427959 T DE 69427959T DE 69427959 D1 DE69427959 D1 DE 69427959D1
Authority
DE
Germany
Prior art keywords
integrated circuit
improved contact
contact barrier
barrier
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69427959T
Other languages
English (en)
Other versions
DE69427959T2 (de
Inventor
Liao De-Dul
Lin Yih-Shung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69427959D1 publication Critical patent/DE69427959D1/de
Application granted granted Critical
Publication of DE69427959T2 publication Critical patent/DE69427959T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/924—Active solid-state devices, e.g. transistors, solid-state diodes with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap
DE69427959T 1994-04-29 1994-12-22 Integrierte Schaltung mit verbesserter Kontaktbarriere Expired - Fee Related DE69427959T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/235,099 US5514908A (en) 1994-04-29 1994-04-29 Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries

Publications (2)

Publication Number Publication Date
DE69427959D1 true DE69427959D1 (de) 2001-09-20
DE69427959T2 DE69427959T2 (de) 2002-04-11

Family

ID=22884099

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427959T Expired - Fee Related DE69427959T2 (de) 1994-04-29 1994-12-22 Integrierte Schaltung mit verbesserter Kontaktbarriere

Country Status (4)

Country Link
US (4) US5514908A (de)
EP (1) EP0680077B1 (de)
JP (1) JPH07312354A (de)
DE (1) DE69427959T2 (de)

Families Citing this family (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514908A (en) 1994-04-29 1996-05-07 Sgs-Thomson Microelectronics, Inc. Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries
JP3280803B2 (ja) * 1994-08-18 2002-05-13 沖電気工業株式会社 半導体装置及びその製造方法
JP3586899B2 (ja) * 1994-09-22 2004-11-10 ソニー株式会社 半導体装置およびその製造方法
US5773363A (en) * 1994-11-08 1998-06-30 Micron Technology, Inc. Semiconductor processing method of making electrical contact to a node
US5858184A (en) * 1995-06-07 1999-01-12 Applied Materials, Inc. Process for forming improved titanium-containing barrier layers
US5972178A (en) * 1995-06-07 1999-10-26 Applied Materials, Inc. Continuous process for forming improved titanium nitride barrier layers
US5736192A (en) * 1995-07-05 1998-04-07 Fujitsu Limited Embedded electroconductive layer and method for formation thereof
US6891269B1 (en) * 1995-07-05 2005-05-10 Fujitsu Limited Embedded electroconductive layer structure
US6238533B1 (en) 1995-08-07 2001-05-29 Applied Materials, Inc. Integrated PVD system for aluminum hole filling using ionized metal adhesion layer
US5962923A (en) * 1995-08-07 1999-10-05 Applied Materials, Inc. Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches
KR100187669B1 (ko) * 1996-01-30 1999-06-01 김주용 반도체 소자의 확산 방지막 형성 방법
EP1028173A3 (de) * 1996-02-26 2000-11-02 Applied Materials, Inc. Barriereschichten aus Titannitrid
US5895266A (en) 1996-02-26 1999-04-20 Applied Materials, Inc. Titanium nitride barrier layers
EP0846783A4 (de) * 1996-03-27 2000-02-02 Sumitomo Sitix Of Amagasaki In Verfahren zur farbentwicklung bei metallischem titan und verfahren zur herstellung von schwarzem und farbigem titan
US5661085A (en) * 1996-06-17 1997-08-26 Chartered Semiconductor Manufacturing Pte, Ltd. Method for forming a low contact leakage and low contact resistance integrated circuit device electrode
JPH10125627A (ja) * 1996-10-24 1998-05-15 Fujitsu Ltd 半導体装置の製造方法および高融点金属ナイトライド膜の形成方法
US6016012A (en) * 1996-11-05 2000-01-18 Cypress Semiconductor Corporation Thin liner layer providing reduced via resistance
GB2319532B (en) * 1996-11-22 2001-01-31 Trikon Equip Ltd Method and apparatus for treating a semiconductor wafer
GB2319533B (en) 1996-11-22 2001-06-06 Trikon Equip Ltd Methods of forming a barrier layer
CA2191260A1 (en) * 1996-11-26 1998-05-26 Luc Ouellet Stabilization of the interface between tin and a1 alloys
US5932907A (en) * 1996-12-24 1999-08-03 International Business Machines Corporation Method, materials, and structures for noble metal electrode contacts to silicon
US6077782A (en) * 1997-02-28 2000-06-20 Texas Instruments Incorporated Method to improve the texture of aluminum metallization
US5858873A (en) * 1997-03-12 1999-01-12 Lucent Technologies Inc. Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof
US6107195A (en) * 1997-06-18 2000-08-22 Tokyo Electron Limited Method for depositing a low-resistivity titanium-oxynitride (TiON) film that provides for good texture of a subsequently deposited conductor layer
KR19990003495A (ko) * 1997-06-25 1999-01-15 김영환 반도체 소자의 베리어 금속층 형성방법
US5926734A (en) * 1997-08-05 1999-07-20 Motorola, Inc. Semiconductor structure having a titanium barrier layer
JP3277855B2 (ja) * 1997-08-27 2002-04-22 ヤマハ株式会社 半導体装置の配線形成方法
JPH11317452A (ja) * 1997-08-29 1999-11-16 Seiko Epson Corp 半導体装置およびその製造方法
US6136677A (en) * 1997-09-25 2000-10-24 Siemens Aktiengesellschaft Method of fabricating semiconductor chips with silicide and implanted junctions
US5989984A (en) * 1997-10-07 1999-11-23 Lucent Technologies, Inc. Method of using getter layer to improve metal to metal contact resistance at low radio frequency power
US6156647A (en) * 1997-10-27 2000-12-05 Applied Materials, Inc. Barrier layer structure which prevents migration of silicon into an adjacent metallic layer and the method of fabrication of the barrier layer
US7253109B2 (en) * 1997-11-26 2007-08-07 Applied Materials, Inc. Method of depositing a tantalum nitride/tantalum diffusion barrier layer system
US20050272254A1 (en) * 1997-11-26 2005-12-08 Applied Materials, Inc. Method of depositing low resistivity barrier layers for copper interconnects
WO1999027579A1 (en) * 1997-11-26 1999-06-03 Applied Materials, Inc. Damage-free sculptured coating deposition
JPH11186190A (ja) * 1997-12-25 1999-07-09 Sharp Corp 半導体装置の製造方法
KR100458297B1 (ko) * 1997-12-31 2005-02-24 주식회사 하이닉스반도체 반도체소자의금속배선형성방법
US6215186B1 (en) * 1998-01-12 2001-04-10 Texas Instruments Incorporated System and method of forming a tungstein plug
US5985759A (en) * 1998-02-24 1999-11-16 Applied Materials, Inc. Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers
JP3374901B2 (ja) * 1998-02-27 2003-02-10 日本電気株式会社 半導体装置
KR100279300B1 (ko) * 1998-05-11 2001-02-01 윤종용 금속 배선 연결 방법
JP3625652B2 (ja) * 1998-06-30 2005-03-02 シャープ株式会社 半導体装置の製造方法
US6110818A (en) * 1998-07-15 2000-08-29 Philips Electronics North America Corp. Semiconductor device with gate electrodes for sub-micron applications and fabrication thereof
KR100331545B1 (ko) 1998-07-22 2002-04-06 윤종용 다단계 화학 기상 증착 방법에 의한 다층 질화티타늄막 형성방법및 이를 이용한 반도체 소자의 제조방법
US6060383A (en) * 1998-08-10 2000-05-09 Nogami; Takeshi Method for making multilayered coaxial interconnect structure
US6208004B1 (en) 1998-08-19 2001-03-27 Philips Semiconductor, Inc. Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof
EP1092239A1 (de) * 1998-08-21 2001-04-18 Micron Technology, Inc. Feldeffekttransistoren, integrierte verdrahtungen, methoden zur herstellung von feldeffekttransistorgates und methoden zur herstellung von intergrierten verdrahtungen
US6410986B1 (en) * 1998-12-22 2002-06-25 Agere Systems Guardian Corp. Multi-layered titanium nitride barrier structure
US6316353B1 (en) * 1999-02-18 2001-11-13 Micron Technology, Inc. Method of forming conductive connections
KR100325302B1 (ko) * 1999-06-16 2002-02-21 김영환 반도체 소자의 제조방법
US6080657A (en) * 1999-07-16 2000-06-27 Taiwan Semiconductor Manufacturing Company Method of reducing AlCu hillocks
US6337151B1 (en) * 1999-08-18 2002-01-08 International Business Machines Corporation Graded composition diffusion barriers for chip wiring applications
US6281543B1 (en) 1999-08-31 2001-08-28 Micron Technology, Inc. Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same
US6316132B1 (en) * 1999-09-02 2001-11-13 Xilinx, Inc. Structure and method for preventing barrier failure
US6824825B2 (en) * 1999-09-13 2004-11-30 Tokyo Electron Limited Method for depositing metallic nitride series thin film
US6544882B1 (en) 2000-01-13 2003-04-08 Taiwan Semiconductor Manufacturing Company Method to improve reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and aluminum-copper-TiN layers in integrated circuits
KR100363013B1 (ko) * 2000-06-28 2002-11-29 삼성전자 주식회사 반도체 장치의 금속 패턴 형성 방법
US6750156B2 (en) 2001-10-24 2004-06-15 Applied Materials, Inc. Method and apparatus for forming an anti-reflective coating on a substrate
KR100564605B1 (ko) * 2004-01-14 2006-03-28 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
KR100446300B1 (ko) * 2002-05-30 2004-08-30 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
US20080070405A1 (en) * 2002-05-30 2008-03-20 Park Jae-Hwa Methods of forming metal wiring layers for semiconductor devices
JP2006019455A (ja) * 2004-06-30 2006-01-19 Nec Electronics Corp 半導体装置およびその製造方法
US7226858B2 (en) * 2004-09-30 2007-06-05 Microchip Technology Incorporated Submicron contact fill using a CVD TiN barrier and high temperature PVD aluminum alloy deposition
US7256121B2 (en) * 2004-12-02 2007-08-14 Texas Instruments Incorporated Contact resistance reduction by new barrier stack process
PT1674117T (pt) * 2004-12-24 2018-11-26 Hexacath Peça mecânica com deformabilidade melhorada
JP2006303063A (ja) * 2005-04-19 2006-11-02 Elpida Memory Inc 半導体装置の製造方法
US7498270B2 (en) * 2005-09-30 2009-03-03 Tokyo Electron Limited Method of forming a silicon oxynitride film with tensile stress
AU2008316630A1 (en) 2007-10-25 2009-04-30 Dexcom, Inc. Systems and methods for processing sensor data
US7727882B1 (en) * 2007-12-17 2010-06-01 Novellus Systems, Inc. Compositionally graded titanium nitride film for diffusion barrier applications
US8119540B2 (en) * 2008-03-28 2012-02-21 Tokyo Electron Limited Method of forming a stressed passivation film using a microwave-assisted oxidation process
US7807586B2 (en) * 2008-03-28 2010-10-05 Tokyo Electron Limited Method of forming a stressed passivation film using a non-ionizing electromagnetic radiation-assisted oxidation process
US8686562B2 (en) 2009-08-25 2014-04-01 International Rectifier Corporation Refractory metal nitride capped electrical contact and method for frabricating same
US9390909B2 (en) 2013-11-07 2016-07-12 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US8772159B2 (en) * 2012-02-01 2014-07-08 United Microelectronics Corp. Method of fabricating electrical contact
US9530736B2 (en) * 2014-02-14 2016-12-27 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US9478438B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US20170170215A1 (en) * 2015-12-15 2017-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with anti-acid layer and method for forming the same
JP6576235B2 (ja) * 2015-12-21 2019-09-18 東京エレクトロン株式会社 Ｄｒａｍキャパシタの下部電極およびその製造方法
US10147782B2 (en) 2016-07-18 2018-12-04 International Business Machines Corporation Tapered metal nitride structure
WO2018117255A1 (ja) * 2016-12-22 2018-06-28 昭和電工株式会社 酸素還元触媒
US10453747B2 (en) * 2017-08-28 2019-10-22 Globalfoundries Inc. Double barrier layer sets for contacts in semiconductor device
EP3762520A4 (de) * 2018-03-09 2021-12-01 The Government of the United States of America, as represented by the Secretary of the Navy Hochtemperatur-gesputterte stöchiometrische titannitrid-dünnschichten
US11152455B2 (en) * 2019-09-23 2021-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method to reduce breakdown failure in a MIM capacitor
US11145710B1 (en) * 2020-06-26 2021-10-12 Micron Technology, Inc. Electrode/dielectric barrier material formation and structures
US11430729B2 (en) 2020-09-16 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. MIM capacitor with a symmetrical capacitor insulator structure
CN114088261A (zh) * 2021-11-22 2022-02-25 中国电子科技集团公司第四十八研究所 一种氮氧化钛薄膜压力传感器及其制造方法
US20230261082A1 (en) * 2022-02-14 2023-08-17 Nanya Technology Corporation Contact strcutre and method for preparing the same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4676866A (en) * 1985-05-01 1987-06-30 Texas Instruments Incorporated Process to increase tin thickness
US4690730A (en) * 1986-03-07 1987-09-01 Texas Instruments Incorporated Oxide-capped titanium silicide formation
US4957590A (en) * 1988-02-22 1990-09-18 Texas Instruments Incorporated Method for forming local interconnects using selective anisotropy
JPH0666287B2 (ja) * 1988-07-25 1994-08-24 富士通株式会社 半導体装置の製造方法
US4998157A (en) * 1988-08-06 1991-03-05 Seiko Epson Corporation Ohmic contact to silicon substrate
US5070036A (en) * 1989-01-04 1991-12-03 Quality Microcircuits Corporation Process for contacting and interconnecting semiconductor devices within an integrated circuit
US5162262A (en) * 1989-03-14 1992-11-10 Mitsubishi Denki Kabushiki Kaisha Multi-layered interconnection structure for a semiconductor device and manufactured method thereof
JPH03153024A (ja) * 1989-11-10 1991-07-01 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5232871A (en) * 1990-12-27 1993-08-03 Intel Corporation Method for forming a titanium nitride barrier layer
US5175126A (en) * 1990-12-27 1992-12-29 Intel Corporation Process of making titanium nitride barrier layer
JPH04259242A (ja) * 1991-02-14 1992-09-14 Fujitsu Ltd 半導体装置の製造方法
JPH0536627A (ja) * 1991-08-01 1993-02-12 Sony Corp 配線形成方法
EP0545602A1 (de) * 1991-11-26 1993-06-09 STMicroelectronics, Inc. Herstellungsverfahren von metallischen Barriere-Schichten
KR0126457B1 (ko) * 1992-01-08 1997-12-26 기타오카 다카시 집적회로, 그 제조방법 및 그 박막형성장치
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
US5371042A (en) * 1992-06-16 1994-12-06 Applied Materials, Inc. Method of filling contacts in semiconductor devices
JP3407204B2 (ja) * 1992-07-23 2003-05-19 オリンパス光学工業株式会社 強誘電体集積回路及びその製造方法
KR960010056B1 (ko) * 1992-12-10 1996-07-25 삼성전자 주식회사 반도체장치 및 그 제조 방법
US5514908A (en) * 1994-04-29 1996-05-07 Sgs-Thomson Microelectronics, Inc. Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries

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US5514908A (en) 1996-05-07
EP0680077B1 (de) 2001-08-16
US5652464A (en) 1997-07-29
US6191033B1 (en) 2001-02-20
JPH07312354A (ja) 1995-11-28
US6291344B1 (en) 2001-09-18
EP0680077A1 (de) 1995-11-02
DE69427959T2 (de) 2002-04-11

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