DE69432200T2 - Als Zellenmatrix-Netzwerk organisiertes elektronisches System - Google Patents

Als Zellenmatrix-Netzwerk organisiertes elektronisches System

Info

Publication number
DE69432200T2
DE69432200T2 DE69432200T DE69432200T DE69432200T2 DE 69432200 T2 DE69432200 T2 DE 69432200T2 DE 69432200 T DE69432200 T DE 69432200T DE 69432200 T DE69432200 T DE 69432200T DE 69432200 T2 DE69432200 T2 DE 69432200T2
Authority
DE
Germany
Prior art keywords
network
cell
electronic system
function
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69432200T
Other languages
English (en)
Other versions
DE69432200D1 (de
Inventor
Daniel Mange
Eduardo Sanchez
Pierre Marchal
Christian Piguet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ecole Polytechnique Federale de Lausanne EPFL
Original Assignee
Ecole Polytechnique Federale de Lausanne EPFL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ecole Polytechnique Federale de Lausanne EPFL filed Critical Ecole Polytechnique Federale de Lausanne EPFL
Publication of DE69432200D1 publication Critical patent/DE69432200D1/de
Application granted granted Critical
Publication of DE69432200T2 publication Critical patent/DE69432200T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
DE69432200T 1993-05-24 1994-05-20 Als Zellenmatrix-Netzwerk organisiertes elektronisches System Expired - Fee Related DE69432200T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH01555/93A CH688425A5 (fr) 1993-05-24 1993-05-24 Circuit électronique organisé en réseau matriciel de cellules.

Publications (2)

Publication Number Publication Date
DE69432200D1 DE69432200D1 (de) 2003-04-10
DE69432200T2 true DE69432200T2 (de) 2003-12-18

Family

ID=4213160

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69432200T Expired - Fee Related DE69432200T2 (de) 1993-05-24 1994-05-20 Als Zellenmatrix-Netzwerk organisiertes elektronisches System

Country Status (6)

Country Link
US (1) US5508636A (de)
EP (1) EP0626760B1 (de)
JP (1) JPH07141408A (de)
AT (1) ATE233970T1 (de)
CH (1) CH688425A5 (de)
DE (1) DE69432200T2 (de)

Families Citing this family (21)

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US5592102A (en) * 1995-10-19 1997-01-07 Altera Corporation Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
US5991907A (en) * 1996-02-02 1999-11-23 Lucent Technologies Inc. Method for testing field programmable gate arrays
FR2748168B1 (fr) * 1996-04-26 1998-06-12 Suisse Electronique Microtech Systeme electronique organise en un reseau matriciel de cellules fonctionnelles
SE507127C3 (sv) * 1996-12-20 1998-05-04 Ericsson Telefon Ab L M Metoder och anordning vid kretskortskonstruktion
US5796994A (en) * 1997-01-30 1998-08-18 Vlsi Technology, Inc. Patch mechanism for allowing dynamic modifications of the behavior of a state machine
US6091258A (en) * 1997-02-05 2000-07-18 Altera Corporation Redundancy circuitry for logic circuits
US6034536A (en) * 1997-02-05 2000-03-07 Altera Corporation Redundancy circuitry for logic circuits
US5916179A (en) * 1997-04-18 1999-06-29 Sharrock; Nigel System and method for reducing iatrogenic damage to nerves
JP3865789B2 (ja) * 1997-05-23 2007-01-10 アルテラ コーポレイション インタリーブされた入力回路を備えるプログラマブル論理装置のための冗長回路
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6202182B1 (en) 1998-06-30 2001-03-13 Lucent Technologies Inc. Method and apparatus for testing field programmable gate arrays
US6201404B1 (en) 1998-07-14 2001-03-13 Altera Corporation Programmable logic device with redundant circuitry
US6256758B1 (en) 1999-03-03 2001-07-03 Agere Systems Guardian Corp. Fault tolerant operation of field programmable gate arrays
US6658618B1 (en) * 1999-09-02 2003-12-02 Polycom, Inc. Error recovery method for video compression coding using multiple reference buffers and a message channel
US6631487B1 (en) 1999-09-27 2003-10-07 Lattice Semiconductor Corp. On-line testing of field programmable gate array resources
US6550030B1 (en) 1999-09-27 2003-04-15 Lattice Semiconductor Corp. On-line testing of the programmable logic blocks in field programmable gate arrays
US6574761B1 (en) 1999-09-27 2003-06-03 Lattice Semiconductor Corp. On-line testing of the programmable interconnect network in field programmable gate arrays
US6530049B1 (en) 2000-07-06 2003-03-04 Lattice Semiconductor Corporation On-line fault tolerant operation via incremental reconfiguration of field programmable gate arrays
US6732348B1 (en) * 2001-09-07 2004-05-04 Xilinx, Inc. Method for locating faults in a programmable logic device
US7685485B2 (en) * 2003-10-30 2010-03-23 Altera Corporation Functional failure analysis techniques for programmable integrated circuits
JP2008164361A (ja) * 2006-12-27 2008-07-17 Mitsubishi Electric Corp 半導体デバイスのマッピング装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4047163A (en) * 1975-07-03 1977-09-06 Texas Instruments Incorporated Fault-tolerant cell addressable array
SU661793A1 (ru) * 1976-03-26 1979-05-05 Ордена Ленина Институт Проблем Управления Способ перестройки однородной структуры с неисправными чейками при реализации вычислительных устройств
US4551814A (en) * 1983-12-12 1985-11-05 Aerojet-General Corporation Functionally redundant logic network architectures
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
JPS61264599A (ja) * 1985-05-16 1986-11-22 Fujitsu Ltd 半導体記憶装置
CA1269726A (en) * 1985-09-11 1990-05-29 Pilkington Micro-Electronics Limited Semi-conductor integrated circuits/systems
US4739250A (en) * 1985-11-20 1988-04-19 Fujitsu Limited Semiconductor integrated circuit device with test circuit
US4700187A (en) * 1985-12-02 1987-10-13 Concurrent Logic, Inc. Programmable, asynchronous logic cell and array
US4918440A (en) * 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
JPS63217821A (ja) * 1987-03-06 1988-09-09 Toshiba Corp 半導体集積回路
US5208491A (en) * 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
US5434514A (en) * 1992-11-19 1995-07-18 Altera Corporation Programmable logic devices with spare circuits for replacement of defects

Also Published As

Publication number Publication date
DE69432200D1 (de) 2003-04-10
EP0626760B1 (de) 2003-03-05
EP0626760A2 (de) 1994-11-30
ATE233970T1 (de) 2003-03-15
JPH07141408A (ja) 1995-06-02
EP0626760A3 (de) 1996-12-11
CH688425A5 (fr) 1997-09-15
US5508636A (en) 1996-04-16

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL), L

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee